Self-test digital phase-locked loop and method thereof

Details Self-test digital phase-locked loop and method thereof Self-test digital phase-locked loop and method thereof

2007-11-06

2007-11-06

Chang, Joseph (Department: 2817)

Oscillators

With frequency calibration or testing

C331S00100A, C375S376000

Reexamination Certificate

active

11294391

ABSTRACT:
A phase-locked loop (PLL) apparatus utilizes a digital control unit to perform a stable phase-locking and self-testing. The PLL circuit internally generates a set of digital parameters. The set of digital parameters are configured to be as the basis of testing. Therefore, the PLL can be tested by a digital way instead of an analog way. In addition, a method of locking a PLL includes three operating modes, and the data capture circuit captures some data generated by phase-locked loop (PLL) during these operation.

REFERENCES:
patent: 2004/0146098 (2004-07-01), Eliezer et al.
patent: 2004/0146132 (2004-07-01), Staszewski et al.

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