Self-test design methodology and technique for root-gated...

Details Self-test design methodology and technique for root-gated... Self-test design methodology and technique for root-gated...

2009-03-11

2010-11-09

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000, C327S239000, C327S242000, C327S415000

Reexamination Certificate

active

07830195

ABSTRACT:
In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

REFERENCES:
patent: 6448835 (2002-09-01), Douskey et al.
patent: 2008/0169848 (2008-07-01), Douskey et al.

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