Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2005-08-09
2005-08-09
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S117000
Reexamination Certificate
active
06928377
ABSTRACT:
Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.
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Eustis Steven M.
Mondal Krishnendu
Ouellette Michael R.
Rowland Jeremy P.
Barlow John
Scully Scott Murphy & Presser
Steinberg William H.
Washburn Douglas N.
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