Cryptography – Communication system using cryptography – Data stream/substitution enciphering
Patent
1985-09-25
1989-02-21
Buczinski, Stephen C.
Cryptography
Communication system using cryptography
Data stream/substitution enciphering
380 44, 380 46, 380 47, H04K 102, H04L 904
Patent
active
048072907
DESCRIPTION:
BRIEF SUMMARY
CROSS REFERENCE TO RELATED APPLICATION
This application is related to application Ser. No. 784,685 filed Sept. 25, 1985.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self-synchronizing scrambler which comprises n clock shift register stages for generating a signal having a scrambler period of 2.sup.n -1 bits, whereby the output of at least one shift register stage is connected to the input of a modulo-2 adder.
2. Description of the Prior Art
Pulse patterns which have a disturbing DC component or whose energy component is particularly high at certain discrete frequencies can occur in digital signal transmission. In order to avoid these pulse patterns, the digital signal to be transmitted is scrambled at the transmitting side by a modulo-2 addition with a pseudo-random sequence. The descrambling occurs at the receiving side by a further modulo-2 addition with the pseudo-random sequence which was employed at the transmitting side. The synchronization of the pseudo-random generators employed at the transmitting and receiving sides, which is thereby necessary, can be avoided by employing free-wheeling and, therefore, self-synchronizing scrambler and descrambler arrangements.
The expansion of digital telecommunications networks has lead to the installation of transmission devices for signals having very high modulation rates between central points of the network. Resulting therefrom, however, is the necessity of constructing scramblers and descramblers for digital signals having a high clock frequency.
"Siemens Forschungs-und Entwicklungsberichte", Vol. 6, No. 1, 1977, pp. 1-5, fully incorporated herein by this reference, discloses a possibility for constructing scramblers for pulse code modulated (PCM) signals having a high clock frequency. The PCM signals having a high bit sequence are scrambled in a plurality of parallel channels having a lower bit repetition frequency and the signals which arise are combined by multiplexing. The receiving side is constructed in an analogous manner, the parallel descrambling occurring in a plurality of channels following a demultiplexer. In addition to the high expense, the necessity of synchronizing multiplexers and demultiplexers with one another therefore also arises.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a suitable self-synchronizing scrambler for the transmission of digital signals having a high bit repetition frequency which, given relatively low expense, omits multiplexing devices.
In a self-synchronizing scrambler of the type initially set forth, the above object is achieved, according to the present invention in a self-synchronizing scrambler which is characterized in that n parallel inputs for each of n parallel bits of the digital signal to be scrambled are provided; in that the inputs are ordered corresponding to the sequence of the incoming bits with the n.sup.th bit at the first input and the following bits at the next inputs and are connected to respective scrambler stages; in that the scrambler stages respectively contain a shift register stage as well as a first modulo-2 adder and a second modulo-2 -adder and the output of the shift register stage is connected to the first input of the first modulo-2 adder and its output is connected to the first input of the second modulo-2 adder; in that the second input of the second modulo-2 adder is connected to the assigned input for the digital signal; and in that the output of the second modulo-2 adder is connected to the input of the shift register stage contained in the same scrambler stage. Furthermore, the invention is characterized in that the second input of the first modulo-2 adder of the one scrambler stage is connected to the output of the shift register stage of the scrambler stage for the m.sup.th bit in all scrambler stages up to the (n-m+1).sup.th scrambler stage; in that m is smaller than n and is a whole number; in that, in the (n-m).sup.th scrambler stage, the connection from the second input of the first modulo-2 a
REFERENCES:
"Parallel arbeitende Scrambler, Descrambler und Zufallsfolgen-Generation", Elektronik Arbeitsblatt Nr. 163, pp. 67-70, 12/30/83.
Mohrmann, K. H., "Realisierung von Scramblern fur PCM Signale hoher Taktfrequenz", Siemens Forsch--u (see p. 2).
Hermes et al., "Parallel arbeitende Scrambler, Descrambler und Zufallsfolgen--Generatoren", (see p. 2).
Entwickl.-Ber., vol. 6, No. 1, 1977, pp. 1-5.
Elektronik, vol. 32, No. 26, Dec. 1983, pp. 67-70.
Buczinski Stephen C.
Gregory Bernarr Earl
Siemens Aktiengesellschaft
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