Self-synchronizing scrambler

Details Self-synchronizing scrambler Self-synchronizing scrambler

1985-05-31

1988-05-10

Cangialosi, Salvatore

Cryptography

Key management

Having particular key generator

380 50, H04L 900

Patent

active

047441046

ABSTRACT:
A self-synchronizing scrambler for high bit rates has a number of scrambler stages supplied in parallel with bits of a signal to be scrambled, each scrambler stage having a series-connected pair of modulo-2 adders, and at least one shift register. A selected number of scrambler stages in the scrambler may include an additional shift register depending upon the number p of parallel bits in the signal to be scrambled, and the total number n of shift registers in the scrambler. The number of scrambler stages having two shift registers is n-p and the number of following scrambler stages having one shift register is 2 p-n. For suppressing short periods, a further modulo-2 adder can be connected between the original two modulo-2 adders, the additional modulo-2 adder inverting at least one bit of the signal for the short periods.

REFERENCES:
"Parallel Arbeitende Scrambler, Descrambler und Zufallsfolgen-Generation", Electronik Arbeitsblatt Nr. 163, pp. 67-70 12/30/83.

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