Self-synchronizing descrambler

Details Self-synchronizing descrambler Self-synchronizing descrambler

1985-07-12

1987-05-05

Cangialosi, Salvatore

Telegraphy

Systems

Printing

178 2217, H04L 900

Patent

active

046635017

ABSTRACT:
A self-synchronizing descrambler for high bit rates having a number of parallel operating descrambler stages each of which represents the series connection of first and second modulo-2 adders and at least one shift register stage for the suppression of short periods between the first and second modulo-2 adders, a third modulo-2 adder is interposed which serves to invert at least one bit of the through going signal on the occurrence of a short. The invention can be used as an alternative to existing descramblers with the processing speed being reduced to a fraction of the previous speed, thus, permitting the use of cheaper semiconductor technology (CMOS).

REFERENCES:
"Parallel asbeitende Scrambler, Descrambler und Zufallsfolgen-Generation", Elektronik Arbeitsplatt No. 163, pp. 67-70, 12/30/83.
Realisierung von Scramblern fur PCM-Signale Hoher Taktfrequenz K. H. Mohramann-Springer-Verlag 1977, vol. 6, No. 1, pp. 1-5.
NTZ 1974 Heft-12 Bit Sequence Independence Through Scramblers in Digital Communications Systems by Horst Muller, Munich pp. 475-479.
A Self-Synchronizing Parallel Scrambler for High Digit Rate Transmission Sytems Using AMI as a Line Code, O. Brugia G. Campanini, S. Improta, R. Pietroiusti, W. Wolfowicz 1981 IEEE pp. #8.6.1-E8.6.5.

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