Self synchronized multiplexer/demultiplexer

Details Self synchronized multiplexer/demultiplexer Self synchronized multiplexer/demultiplexer

1979-11-09

1981-11-10

Olms, Doulgas W.

Multiplex communications

Wide area network

Packet switching

370112, H04J 306

Patent

active

043002323

ABSTRACT:
This multiplexer and demultiplexer features two transmission lines, one for conveying the data and a second for timing. The timing line controls both the shifting of data in the demultiplexer and the signaling for the beginning and end of data words. Synchronization of the bit shifting clock with the word shifting signal is accomplished by means of phase lock loop circuitry incorporated into the demultiplexer. The disclosed circuit uses low power CMOS design, directly interfaces with contact closure commands, and directly drives relay or lamp type loads. The demultiplexer contains a power-up delay circuit to avoid start-up ambiguities and false data transmission.

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