Self-synchronized, multi-sample, quadrature phase detector

Details Self-synchronized, multi-sample, quadrature phase detector Self-synchronized, multi-sample, quadrature phase detector

2000-10-02

2002-04-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S012000

Reexamination Certificate

active

06373293

ABSTRACT:

BACKGROUND
The present invention relates to phase detectors, phase-locked loops, and delay-locked loops.
Phase detectors, which detect a phase relationship between plural signals, may be found in various systems, including communications systems, computers, and memory devices. Phase detectors may be used, for example, to synchronize signals for data transmission or reception by detecting relative phases of signals so that the phases can be adjusted to achieve a desired result. Phase detectors are commonly used, for example, as a part of a phase-locked loop (PLL) or delay-locked loop (DLL). Both PLLs and DLLs generally offer the ability to delay the phase of a signal by an amount that may be in a range between 0° and 360°. Typically, PLLs are employed to recover a clock signal or to multiply a signal from a slow frequency to a high frequency, whereas DLLs are used for precise alignment of signals.
A first type of phase detector may be called a zero phase detector, and simply detects and reports whether one signal was early or late compared to another. This can be made with a fairly straightforward circuit, for the phase difference is merely a function of the relative position of the edges of the signals, and is largely independent of the frequency of oscillation.
For high-frequency, low-voltage or high-noise signals, it may be desirable to detect a signal at the midpoint of another signal, rather than attempting to align edges for detection. A quadrature phase detector (QPD) attempts to detect a phase difference between a midpoint of one signal and an edge of another. Stated differently, a QPD detects whether two signals are 90° out of phase with each other, and if not, the relative variance of the signals from that 90° phase relationship. A challenge in designing a QPD is that aligning an edge of one pulse with the midpoint of another pulse implies some processing of pulse duration or frequency in order to determine that midpoint. Determining a pulse midpoint becomes more difficult with increasing signal frequency and reduced pulse voltage levels.
A prior art QPD circuit is shown in
FIG. 1
, and clock signals C and D, whose phases are being compared by the QPD, are shown in FIG.
2
. The QPD includes a first current source
20
that provides charge to a first capacitor
22
during a time when signal C is high and signal D is low, such as period T
1
. The amount of charge that has built up on capacitor
22
results in a voltage on that capacitor that is an indication of the duration of period T
1
. A switch
25
can then be closed to reset the voltage across capacitor
22
to zero volts, so that charge build up on the capacitor can be used again to measure the duration of other periods when signal C is high and signal D is low. Similarly, current source
30
provides charge onto a capacitor
33
during a time when signal C is high and signal D is also high, for example period T
2
. The voltage that has built up on capacitor
33
is thus an indication of the duration of period T
2
. A switch
35
can then reset the voltage across capacitor
33
to zero volts, so that the charge build up on the capacitor can be used again to measure the relative duration of other times when both signals C and D are high. A comparator
40
has inputs connected to capacitor
22
and capacitor
33
for determining whether time T
1
is greater or less than time period T
2
, and adjusts the phase of C or D accordingly to attempt to make later pulses have a quadrature phase relationship, which is again measured at times T
3
and T
4
.
In order to operate the QPD, the frequency of signal C is divided by three, to produce signal C/
3
, which is then compared with signal C to generate signals R, I and S. Reset signal R is high for a time during which the switches
25
and
35
are closed to dissipate any charge on capacitors
22
and
33
. While integration signal I is high, the switches are open and charge is allowed to build up on capacitors
22
and
33
. While set signal S is high, the voltage on capacitors
22
and
33
is compared and stored for adjusting the phase.
A disadvantage of the mechanism shown in FIG.
1
and
FIG. 2
is that a phase correction signal is created after looking at only a single pulse cycle, which can cause jitter or oscillations about a desired phase unless additional circuitry is provided for smoothing the shift in phase. Further circuitry is also needed to produce signals R, I and S, and this circuitry also requires additional chip real estate and adds potential sources of error. Moreover, the duration of an individual pulse, such as the time when signal C is high represented by adding T
1
and T
2
, may vary significantly from average, which can cause incorrect adjustments of phase. For high-frequency, low-voltage, or high-noise conditions, or for situations in which the signals being compared differ from perfect square waves, variations of individual pulses from average may be especially pronounced. Further, the phase alignment is only sampled during one-third of the pulses, with the other pulses used for resetting the circuit and measuring or storing the output, thereby ignoring a majority of the data available for phase detection.
SUMMARY
In accordance with the present invention, phase detection circuitry is disclosed that can detect phase differences from a quadrature phase relationship, without the need for extensive additional circuitry for driving and correcting the phase detection circuitry. Such circuitry can measure plural or multiple pulse durations consecutively, without interruption to reset the circuit or store the values generated by the circuit, affording a much higher sampling rate and sampling a higher proportion of pulses than is conventional. Averaging of the phase data samples is also provided by measuring multiple pulses, so that phase changes are not instigated based upon a signal from an individual sample that may differ significantly from the average. In addition to detecting quadrature phase relationships, the phase detection circuitry can be adjusted to compensate for a desired offset in one of the signals from quadrature, or can be set to detect other phase relationships. The phase detection circuitry can also be configured to automatically adjust for variations in temperature, voltage and processing conditions. Each of these attributes is useful for high-frequency, low-voltage, or high-noise signals, so that the phase detection circuitry has a number of advantages for use with such signals, but is by no means limited by this brief summary of possible features.


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patent: WO 99/62217 (1999-12-01), None
Hui Wang, Richard Nottenberg, “A Gb/s CMOS Clock and Data Recovery Circuit,” 1999 IEEE International Solid-State Circuits Conference.

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