Self-synchronization circuit for a FFSK or MSK demodulator

Details Self-synchronization circuit for a FFSK or MSK demodulator Self-synchronization circuit for a FFSK or MSK demodulator

1981-04-03

1983-05-17

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 90, 329 50, 329124, 455208, H03D 318, H03D 324

Patent

active

043843573

ABSTRACT:
The self-synchronization circuit splits the incoming signal into two circuit paths where the signals are frequency shifted by a frequency signal equal to the carrier frequency so as to provide an in-phase signal in one circuit path and a quadrature signal in the other circuit path. The frequency shifting circuit includes at least a controllable oscillator. The output of a first multiplier which multiplies the in-phase and quadrature signals, is fed to a clock recovery circuit which determines the clock frequency. A second multiplier multiplies the output of the first multiplier with the clock recovery circuit output to provide a signal which controls the controllable oscillator. In addition, a frequency discriminator utilizes the in-phase and quadrature signals to initially coarse control the controllable oscillator frequency. The frequency shifting signals may be obtained from the controllable oscillator feeding phase shifting circuits, or they may be obtained from a combined circuit including a fixed oscillator with phase shifting circuits together with the controllable oscillator and appropriate mixing circuits.

REFERENCES:
patent: 3710261 (1973-01-01), Low et al.
patent: 3769589 (1973-10-01), Buntschuh et al.
patent: 3806815 (1974-04-01), Fletcher et al.
patent: 3984778 (1976-10-01), Bhopale
patent: 4057762 (1977-11-01), Namiki
patent: 4143322 (1979-03-01), Shimamura
patent: 4188589 (1980-02-01), Brown et al.
patent: 4213096 (1980-07-01), Daniel, Jr.
patent: 4314206 (1982-02-01), Attwood et al.
patent: 4324001 (1982-04-01), Rhodes

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