Self-switched cascode write driver

Details Self-switched cascode write driver Self-switched cascode write driver

1997-01-09

2002-05-14

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S588000, C360S046000

Reexamination Certificate

active

06388476

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of analog circuits, and, in particular, to write circuitry for magnetic recording systems.
2. Background Art
In magnetic data recording systems, data information is recorded on a disk surface by individually modifying the magnetic orientation of small regions of the disk surface. This modification is performed by placing a strong, localized magnetic field of the desired orientation in close proximity to the selected region of the disk surface. In disk drives, the magnetic field is typically generated by a “write head” suspended from an arm over the disk surface. The write head contains an inductive coil capable of producing a localized electromagnetic field with direction and magnitude dependent on electrical current passed through the inductive coil. Data is written on the disk surface by changing current direction in the writing head. The apparatus used to direct current through the inductive coil of the write head is generally known as a “write driver.”
Typically, H-bridge configurations are used for write drivers. A symbolic diagram of an H-bridge is shown in FIG.
1
A. The inductive head (LHEAD) is coupled across nodes HX and HY. Upper switches S
1
and S
2
couple nodes HX and HY, respectively, to the positive voltage supply (VCC). Lower switches S
3
and S
4
couple nodes HX and HY, respectively, to current source IW. Current source IW is further coupled to a lower voltage supply or ground (GND) node. It is also possible to orient the H-bridge such that the current source is above the upper switches rather than below the lower switches. The upper switch may consist of NPN or PNP bipolar junction transistors (BJTs), or P-type field effect transistors (PFETs). NPN BJTs or Ntype FETs are typically used for the lower switches.
The switches of the write driver are used to steer the write current provided by constant current source IW through the inductor LHEAD. To steer current through LHEAD from node HX to node HY, upper switch S
1
and lower switch S
4
are closed to provide a current path from VCC to GND that passes through LHEAD, while switches S
2
and S
3
are open circuits (as shown in FIG.
1
A). To change the direction of current flow to pass from node HY to node HX, switches S
2
and S
3
are closed, and switches S
1
and S
4
are open.
FIG. 1B
shows a write driver circuit implementation of the prior art. NPN transistors Q
101
and Q
102
correspond to upper switches S
1
and S
2
of FIG.
1
A. Schottky transistors Q
103
and Q
104
correspond to lower switches S
3
and S
4
. The collectors of transistors Q
101
and Q
102
are coupled to VCC. The emitters of transistors Q
101
and Q
102
are coupled to nodes HX and HY, respectively. Resistors R
111
and R
112
are coupled to VCC and to the base junctions of transistors Q
101
and Q
102
, respectively. The collectors of Schottky transistors Q
103
and Q
104
are coupled to nodes HX and HY, respectively. The emitters of Schottky transistors Q
103
and Q
104
are coupled to constant current source IW, which is in turn coupled to ground (GND). The base junction of transistor Q
103
is coupled through resistor R
113
to voltage input WDX. The base junction of transistor Q
104
is coupled through resistor R
114
to voltage input WDY. The collectors of Schottky transistors Q
105
and Q
106
are coupled to the base junctions of transistors Q
101
and Q
102
, respectively. The emitters of transistors Q
105
and Q
106
are coupled together to constant current source I
1
. The base junctions of transistors Q
105
and Q
106
are coupled to voltage inputs WDX and WDY, respectively. Current source I
1
is further coupled to ground.
The circuit of
FIG. 1B
operates from the differential voltage input provided by WDX and WDY. When WDX is at a higher potential than WDY, transistors Q
103
and Q
105
are conducting, whereas transistors Q
104
and Q
106
are not conducting. Transistor Q
105
pulls down the base voltage of transistor Q
101
, shutting off the current through transistor Q
101
. The base junction of transistor Q
102
is pulled near VCC by resistor R
112
, turning on transistor Q
102
. The H-bridge current path consists of transistor Q
102
, inductor LHEAD, transistor Q
103
and current source IW.
When WDY is at a higher potential than WDX, transistors Q
104
and Q
106
are conducting, whereas transistors Q
103
and Q
105
are not conducting. Transistor Q
106
pulls down the base voltage of transistor Q
102
, shutting off the current through transistor Q
102
. The base junction of transistor Q
101
is pulled near VCC by resistor R
111
, turning on transistor Q
101
. The H-bridge current path becomes transistor Q
101
, inductor LHEAD, transistor Q
104
and current source IW.
The Schottky transistors can be modeled as standard NPN transistors with a Schottky diode coupled between the base and collector junctions. The Schottky diode conducts current from the base to the collector when the base-collector voltage of the transistor becomes forward biased and reaches approximately 0.3 volts, depending on the device process. This action serves to clamp the base-collector voltage to a maximum of 0.3 volts. For an active transistor with a base-emitter voltage of 0.7 volts, the collector-emitter voltage may never drop below approximately 0.4 volts. Therefore, the clamped transistor cannot go into saturation and transistor switching speed can be maintained.
Transistors Q
101
and Q
102
do not require Schottky clamping because, in the circuit of
FIG. 1B
, the base-collector voltage of these devices can never exceed zero volts without shutting off the transistor.
Since the write head is an inductor, a certain amount of induced voltage appears across the inductive load. Rise and fall transition times, “t
r
” and “t
f
”, of the head write current are given by the following equation:
t
r
=t
f
=L
h
*&Dgr;I
h
/V
h
where L
h
is the head inductance, &Dgr;I
h
is the change in current and V
h
is the available voltage across the write head, also referred to as the head voltage swing. Because the rise and fall times are inversely related to the head voltage swing, a higher head voltage swing provides shorter rise and fall transition times, e.g. faster performance. Therefore, it is desirable to maximize the available head voltage swing.
The head voltage swing is determined by the voltage range between the upper and lower power supplies that is not taken up by the devices in the current path. In the circuit of
FIG. 1B
, the head voltage swing is set by VCC less the minimum voltage across devices Q
101
, Q
104
and IW (or, equivalently, devices Q
102
, Q
103
and IW). The peak head voltage swing for
FIG. 1B
is given by:
V
h
(peak)=
VCC
−(
V
BE
+V
CE,min
+V
IW
)
where V
h
(peak) is the head voltage swing, V
BE
is the base-emitter voltage of the upper active transistor, V
CE,min
is the minimum collector-emitter voltage of the lower active transistor, and V
IW
is the voltage across current source IW.
One method for improving the head voltage swing in low power applications with voltage supplies at or below five volts is discussed in U.S. Pat. No. 5,386,328 granted to Chiou et al., issued Jan. 31, 1995, and assigned to the assignee of the present invention. A method and apparatus are disclosed in the '328 patent for maximizing the head voltage swing in a limited supply voltage range such as 3.3 volts. The circuit of the '328 patent comprises a current mirror-based write driver. A symbolic diagram of this current mirror-based write driver is shown in FIG.
2
A.
In
FIG. 2A
, upper switches S
1
and S
2
are positioned relative to the head inductor as in FIG.
1
A. However, Switches S
3
and S
4
have been relocated to a parallel current path along with the current source IW
. Coupled between nodes HX and HY and the ground node (GND) are current mirror blocks
210
and
202
, respectively. Switch S
3
is coupled between current source IW
and current mirror
201
. Switch S
4
is coupled between current so

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