Etching a substrate: processes – Planarizing a nonplanar surface
Reexamination Certificate
2000-05-12
2002-03-26
Nguyen, Nam (Department: 1753)
Etching a substrate: processes
Planarizing a nonplanar surface
C438S692000, C430S314000, C204S192170
Reexamination Certificate
active
06361704
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to provide an aluminum pad that covers exposed copper and thereby protect the copper against oxidation.
(2) Description of the Prior Art
This invention relates to the creation of pad structures that are used for integrated circuits. This invention more particularly relates to structures that allow multiple via holes to be used such that they can provide electrical contacts between overlying layers of metal interconnects within a semiconductor device.
In creating semiconductor devices, the technology of interconnecting devices and device features is of great importance. Bond pads are frequently used for this purpose, it is a requirement in creating semiconductor devices that bond pads can be produced that are simple, reliable and inexpensive.
Bond pads are generally used to wire device elements and to provide exposed contact regions of the die, these contact regions are suitable for wiring the die to components that are external to the die. An example is where a bond wire is attached to the bond pad of a semiconductor die at one end and to a portion of a Printed Circuit Board at the other end of the wire. The art is constantly striving to achieve improvements to the creation of bond pads that simplify the manufacturing process while enhancing bond pad reliability.
A frequently used bond pad consists of an exposed aluminum pad. A gold bond wire can be bonded to this aluminum pad. This type of a connection however is highly temperature dependent. At ambient temperatures below about 150 degrees C., the gold of the bond wire will not chemically interact with the aluminum of the pad making the physical attachment and the electrical connection between the gold wire and the aluminum pad sufficiently reliable. At higher temperatures however, above about 150 degrees C., gold starts to interact with the aluminum as a consequence of which the bond rapidly deteriorates. As a result, porosity, delamination and voiding occur within the bond. These effects become more pronounced with the aging of the bond and will eventually result in bond failure. Potential reliability problems therefore prevent using the aluminum bond pad under conditions where the ambient temperature is known to be in excess of 150 degrees C. Furthermore, even when the ambient temperature is less than approximately 150 degrees C., the aluminum bond pad is susceptible to corrosion simply because it is exposed.
Aluminum grows a passivating oxide layer in air and is as a consequence protected against corrosion. Aluminum wiring used in semiconductors, however, contains copper, which does not have a passivating oxide, and the Al—Cu alloy used is more vulnerable to corrosion. The corrosion of aluminum wires is caused by several sources such as chlorine transported through the plastic packaging and the passivation materials, chlorine from the etching compounds and as etching by-products, phosphorous acid formed from excess phosphorous in the phosphosilicate glass, etc. Only a small amount of chlorine is required to cause severe local corrosion of the aluminum lines. Aluminum corrosion can, in addition, occur very quickly after metal etching.
To avoid etching introduced corrosion, chlorine compounds and elemental chlorine must be removed from the metal surface immediately after plasma etching. A water rinse or a water vapor treatment usually accomplishes this.
Modern metal structures use multi-levels of dissimilar materials such as Ti/TiN/Al—Cu/TiN or Ti/Al—Cu/TiN, which increases the possibility of electromechanical corrosion.
Copper is electro-positive with respect to hydrogen and is not vulnerable to corrosion. However, in air copper oxide grows linearly with time, indicating the lack of a protective oxide. This lack of a passivating oxide makes copper more vulnerable to chemical corrosion. To avoid or minimize this corrosion, most applications of copper metalization involve some protective layer deposited on top of the copper.
Materials that are used for bond pads include metallic materials such as tungsten and aluminum while heavily doped polysilicon can also be used for contacting material. The bond pad is formed on the top surface of the semiconductor device whereby the electrically conducting material is frequently embedded in an insulating layer of dielectric. In using polysilicon as the bond pad material, polysilicon can be doped with an n-type dopant for contacting N-regions while it can be doped with p-type dopant for contacting P-regions. This approach; of doping avoids inter-diffusion of the dopants and dopant migration. It is clear that low contact resistance for the bond pad area is required while concerns of avoidance of moisture or chemical solvent absorption, thin film adhesion characteristics, delamination and cracking play an important part in the creation of bond pads.
Methods have been proposed for creating bond caps that require capping of the layer of metal. A barrier layer is thereby deposited over the layer of metal, the barrier layer is patterned after which the barrier layer and the layer of metal are etched. The metal layer is thereby selectively exposed, the bond pad is formed over the barrier layer typically using electrolysis technology.
The conventional processing sequence that is used to create an aluminum pad has been detailed in
FIGS. 1
a
through
1
m.
No processing conditions or materials that are used for the following sequence will be highlighted since these processing conditions and materials all fall within the scope of the present art.
The process starts with a semiconductor surface
10
,
FIG. 1
a,
typically the surface of a silicon single crystalline substrate, in which a copper electrical contact point
12
has been provided. This contact point can be a point of interconnect with a network of metal lines or it can be a contact point or a point to which a via needs to be established. Point
12
can also be an alignment mark that is typically used to position wafers inside semiconductor processing tools. A passivation layer
14
is deposited over the surface
10
,
FIG. 1
b,
an opening overlying the contact point
12
is first created in the passivation layer. For this purpose, a first layer
16
of photoresist,
FIG. 1
c,
is deposited over the passivation layer
14
and exposed using mask
18
. The exposure to the light source
20
makes the photoresist soluble in the area where the light impacts the photoresist, the photoresist can therefore readily be removed over the area of light impact.
FIG. 1
d
shows a cross section after the exposed first photoresist has been removed and the exposed underlying layer
14
of passivation has been etched in accordance with the opening that has been created in the first layer
16
of photoresist. The patterned first layer
16
of photoresist can now be removed resulting in the cross section that is shown in
FIG. 1
e.
The aluminum from which the aluminum pad will be created is next deposited, layer
22
,
FIG. 1
f.
The aluminum layer needs to be patterned, a second layer
24
of photoresist is therefore deposited over the layer
22
of aluminum,
FIG. 1
g.
This second layer
24
of photoresist is exposed by light source
28
via mask
26
,
FIG. 1
h.
The non-exposed second photoresist is removed leaving a layer
24
,
FIG. 1
j,
of second photoresist in place above the layer of aluminum whereby this second photoresist is aligned with the contact point
12
. The layer
22
can now be etched,
FIG. 1
k,
leaving the layer
24
in place above the contact point
12
. Remains the removal of the patterned second layer of photoresist,
FIG. 1
m,
which completes the creation of the aluminum pad
22
overlying the contact point
12
.
The process of creating an aluminum pad as shown under
FIG. 1
, has several significant drawbacks, as follows:
the procedure of
FIGS. 1
a
through
1
m
requires successive alignments of the various etches and exposures to assure that these etches and exp
Shih Tsu
Yu Chen-Hua
Ackerman Stephen B.
Nguyen Nam
Saile George O.
Taiwan Semiconductor Manufacturing Company
VerSteeg Steven H.
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