Electrical generator or motor structure – Dynamoelectric – Rotary
Patent
1998-11-30
2000-10-31
Ramirez, Nestor
Electrical generator or motor structure
Dynamoelectric
Rotary
310168, 310254, H02K 3702
Patent
active
061407313
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to computer networks where calculations are performed on the individual bits of data to determine if an error has occurred during transmission of the data from one device to another. In particular, the present invention relates to a particular method and device for calculating a Frame Check Sequence (FCS) for a frame transmitted across a computer network.
BACKGROUND OF THE INVENTION
Many different types of error checking methods are known. One of the earliest methods is known as a parity check. This requires that each frame of data transmitted across the computer network must have an even number of bits representing the "1" state. All frames sent across the computer network with this system have a parity bit. If a transmitter was to send a frame that had an odd number of 1's, the transmitter would set the parity bit to 1, in order to have the total number of 1's in the frame be equal to an even number. If the transmitter was to send a frame that already had an even number of 1's, the parity bit was set to zero.
When a frame was received, the receiver would count the number of 1's in the frame. If the number of 1's was odd, the receiver knew an error had occurred. If the number of 1's in the received frame was even, the receiver assumed the frame had been received correctly.
While this method of parity checking provides detection of many types of errors, it will not detect all errors occurring during the transmission of a frame. More sophisticated methods have become known to detect a greater number of the different types of errors that are possible. These methods are known as Frame Check Sequences (FCS), and specific information for the type of FCS used in the present invention can be found in the American National Standard for Advanced Data Communication Control Procedures (ADCCP), ANSI X3.66-1979 (Section 12 & Appendix D), and Telecommunications; Synchronous Bit Orientated Data Link Control Procedures (Advanced Data Communications Control Procedures), FED-STD-1003A, available from GSA specification section, 7&D Street, S.W. Washington D.C. 20407, hereby incorporated by reference. These standards analyze the data in a frame, and generate a 32 bit FCS value. This FCS value is then either added to the frame, or checked with the FCS value already present in the frame.
These standards rely on data being transmitted in 8 bit words also known as bytes. All calculations are therefore done with 8 bits of the frame at a time.
Networks are being required to handle ever increasing amounts of data, with faster transmission of data being always beneficial. The calculating of the FCS, is required for each frame that is transmitted and received, and is very important to the operation of the network. The FCS is a significant burden and hinderance to increasing the speed of transmitting large amounts of data over a network.
SUMMARY AND OBJECTS OF THE INVENTION
It is a primary object of the present invention to provide a method and apparatus for generating an FCS in a computer network capable of transmitting data at high data rates.
The present invention accomplishes this objective by dividing the frame conveyed across the network into a plurality of segments, where each segment has an identical number of bits. The number of bits of each segment is greater than 8, and is preferably an integer multiple of 8. All of the bits of a segment are received simultaneously, with each segment of the frame being received sequentially. In this way several bytes can be transmitted and received simultaneously thus greatly increasing the data rate. Very often, the number of bits in the entire frame, will not be an integer multiple of the number of bits in the segment. Therefore the bits of the frame can be unevenly divided into the plurality of segments. The present invention detects the number of bits from the frame that are present in each of the segments, or at least the number of bits of the frame present in the last segment.
An FCS function which operates on 8 bits at a time
REFERENCES:
patent: 4348605 (1982-09-01), Torok
patent: 4672253 (1987-06-01), Tajima et al.
patent: 5117144 (1992-05-01), Torok
patent: 5345131 (1994-09-01), Torok
patent: 5548173 (1996-08-01), Stephenson
patent: 5672925 (1997-09-01), Lipo et al.
patent: 5825112 (1998-10-01), Lipo et al.
Schaer Roland
Torok Vilmos
Wissmach Walter
Nguyen Tran N
Ramirez Nestor
Vilmos Trorok
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