Self-sequencing memory

Communications: electrical – Digital comparator systems

Patent

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Details

340174VB, 340173SP, G06F 906, G11C 506, G11C 1700

Patent

active

039914089

ABSTRACT:
A self-sequenced read only memory is shown wherein each word line contains dynamic logic circuits for energizing a next word line after the fixed time delay provided by the dynamic logic circuits. Self-sequencing inverters are physically placed within the array area thereby increasing reliability and reducing circuit wiring. When used as a microprogram control storage, the memory is divided into a plurality of self-sequenced control routines. When a certain function is to be performed, the first word line of the control routine for performing the selected function is energized. Since each word line includes a one cycle delay and is wired to the next sequential word line, no separate timing or address control is required to address word lines within a selected control routine. Once a control routine is energized, sequential microinstructions will be automatically fetched including branch and branch-on condition instructions. Branch operations can be implemented by connecting one of the outputs of the array to the branched-to word line. Branch-on condition can be implemented by gating the inverter in the branched-to instruction with an AND circuit. By virtue of the self-sequencing of the memory, branched-to word lines can be sequentially accessing memory words simultaneously with sequential memory word fetch operations within the branched from control routine. The branched-to control routine thereby acts as a modifier routine to modify the bit patterns of the memory words which continue to be fetched by the branched-from control routine.

REFERENCES:
patent: 3117309 (1964-01-01), Wolf
patent: 3404385 (1968-10-01), Ihara
patent: 3435438 (1969-03-01), Regitz
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3618051 (1971-11-01), Oleksiak

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