Self-resetting phase/frequency detector with reduced dead zone

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

327 12, 327 5, H03D 1300, H03K 526

Patent

active

059778016

ABSTRACT:
A phase/frequency detector, such as may be used in a phase-lock loop (PLL), having reduced jitter at high frequencies by reducing or eliminating the dead zone. The detector generates two output signals (UP and DOWN) wherein one of the output signals (depending upon which input signal arrives first) has a pulse width which is equal to a time delay between the input signals. There is a dead zone associated with very small phase differences between the input signals, and the dead zone is reduced by increasing the durations of two output pulses, using several delay elements which operate on signals that are derived from the reference and feedback inputs. The circuit may be tuned to reduce the dead zone to less than one picosecond, making it particularly useful for very high speed (greater than one gigahertz) clock circuits. The phase/frequency detector uses self-resetting, complementary metal-oxide semiconducting (SRCMOS) gates. First and second latches may be used to prevent the SRCMOS gates from discharging before a subsequent reset signal.

REFERENCES:
patent: 4354124 (1982-10-01), Shima et al.
patent: 4439278 (1988-04-01), Des Brisay Jr. et al.
patent: 4751469 (1988-06-01), Nakagawa et al.
patent: 4804928 (1989-02-01), Chloupek et al.
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5191239 (1993-03-01), Rogers
patent: 5266851 (1993-11-01), Nukui
patent: 5386437 (1995-01-01), Yasuda
patent: 5422603 (1995-06-01), Soyuer
patent: 5436596 (1995-07-01), Folmer
patent: 5465075 (1995-11-01), Yaklin
patent: 5485125 (1996-01-01), Dufour
patent: 5491439 (1996-02-01), Kelkar et al.
patent: 5546052 (1996-08-01), Austin et al.
patent: 5631582 (1997-05-01), Fukolawa
patent: 5661419 (1997-08-01), Bhagwan
S. Khursheed Enam and Assad A. Abidi, "NMOS IC's for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers," IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992.
Ian A. Young, Jeffrey K. Greason, and Keng L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits, vol. 27 No. 11, Nov. 1992.
Thomas H. Lee, Kevin S. Donnelly, John T.C. Ho, Jared Zerbe, Mark G. Johnson, and Toru Ishikawa, "A. 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM," IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994.
Floyd M. Gardner, Ph.D, "Phaselock Techniques," pp. 123-125.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Self-resetting phase/frequency detector with reduced dead zone does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-resetting phase/frequency detector with reduced dead zone, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-resetting phase/frequency detector with reduced dead zone will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2140472

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.