Self-resetting CMOS parallel adder with a bubble pipelined archi

Details Self-resetting CMOS parallel adder with a bubble pipelined archi Self-resetting CMOS parallel adder with a bubble pipelined archi

1995-06-05

1997-05-27

Mai, Tan V.

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364780, G06F 750

Patent

active

056338201

ABSTRACT:
A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks. A fast cycle time and minimum delay for each block is achieved by using fast forward amplification of the leading edge of the pulsed input signals followed by quick self-resetting of all nodes back to their standby state.

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Chappell et al., "A 2-ns Cycle 3.0-ns Access 512-kb CMOS ECL SRAM with a Fully Architecture" IEEE Journal of Solid-State Circuits vol. 26, No. 11 Nov. 1991, pp. 1577-1585.

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