Self-resetting bypass control for scan test

Details Self-resetting bypass control for scan test Self-resetting bypass control for scan test

1994-11-10

1995-12-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327 18, 327142, 327198, 371 223, 371 225, G01R 1900, H03L 700

Patent

active

054791278

ABSTRACT:
A self-resetting bypass control circuit is disclosed for use with scan testing of integrated circuits. The bypass control circuit includes a shift register and an OR gate. A test-enable signal is input to the shift register and to the OR gate, and the output of the shift register is also input to the OR gate. The output of the OR gate is a bypass signal that goes logic high immediately when the test enable signal goes logic high, that stays logic high while the test enable signal goes logic low momentarily, and that resets to logic low when the test enable signal goes logic low for an extended period of time.

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patent: 5260949 (1993-11-01), Hashizume et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5357572 (1994-10-01), Bianco et al.

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