Self repair large scale integrated circuit

Details Self repair large scale integrated circuit Self repair large scale integrated circuit

1984-12-11

1987-10-06

Smith, Jerry

Excavating

371 8, G06F 1116

Patent

active

046988076

DESCRIPTION:

BRIEF SUMMARY
INTRODUCTION

The sonar signal processing task is characterised by high input/output data rates together with desired computational loads which exceed the capacity of currently available main-frame computers. Adaptive algorithms for various tasks such as beam-forming, filtering, display enhancement, etc. are widely discussed in the journal literature such as the journal of the Acoustical Society of America. These are needed in a real-world environment as they have the potential to significantly enhance the performance of sonar systems in terms of target detection and tracking. However, they increase the computing load by orders of magnitude. Hard wired implementations of some processors with abilities to go some way towards meeting the desired computing load, are constrained in size by a lack of space on the mobile platforms on which they are installed.
The necessary consequence of these conflicting requirements is the matching of software algorithms to efficient hardware realisations. In the past this has implied dedicated hardware as mentioned above. Such hardware is not easily reconfigurable in the event of a fault. Failure in part of the system implies the manual replacement of that part. The necessary operator intervention both for fault diagnosis and part replacement is unacceptable in todays environment.
Current work in the area of high performance, special-purpose computer systems indicates that future sonar processors will have systolic architectures. Software will be implemented on multidimensional VLSI arrays of systolic processing elements (SPE's) where each element is connected to its nearest neighbours only. Descriptions of such architectures, together with applications and performance, have been given by a numer of authors including
(1) Kung H. T., "Why systolic architectures?", COMPUTER, 15, 1, January, 1982,
(2) Whitehouse H. J. and Speiser J. M., "Sonar applications of systolic array technology", IEEE EASCON, Washington, D.C., November, 1981,
(3) Mead C. A. and Conway L. A., "Introduction to VLSI systems", Addison-Wesley, Reading, Mass., 1980,
(4) Snyder L., "Introduction to the configurable, highly parallel computer", COMPUTER, 15, 1, January, 1982, and
(5) Bertram J. F., Ramseyer R. R. and Heins J. M., "Fifth generation digital sonar signal processing", IEEE Journal of Oceanic Engineering, October, 1977.
Consideration of the advantages of this approach to the sonar signal processing problem leads to a necessary consideration of the implications for system reliability. As noted by Snyder L., "Introduction to the configurable, highly parallel computer", COMPUTER, 15, 1, January, 1982, the implementation of a configurable systolic array processor (SAP) leads to a fault tolerant architecture.
In this specification consideration is given to a particular systolic configurable array processor (SCAP) which in the application environment allows the processor to possess a limited self-repair characteristic which does not require operator intervention or down-time in the event of a failure in one or more of its elements. A tentative analysis of the system fault tolerance is provided. For less critical applications it is noted that such an architecture can effectively increase the yield percentage in the production of VLSI dice.


THE INVENTION

The system of this invention generally comprises a module having a series of elements arranged in rows normal to each other with the sequential paths between elements biased in such a way that normally the data being processed follows the vertical and horizontal rows but should one of the elements be unfunctional either through breakdown of the element or the elements being busy, a secondary path is established to an available element in the next row and from this back to follow the row of the initial element through the chip.
A method of this invention comprises a series of systolic processing elements (SPE's) arranged in rows normal to each other, have sequential paths between elements biased so that normally the data being processed follows the vertical

REFERENCES:
patent: 3654610 (1972-04-01), Sander
patent: 3665173 (1972-05-01), Bouricius
patent: 3665418 (1972-05-01), Bouricius
patent: 4438494 (1984-03-01), Budde
patent: 4533993 (1985-08-01), McCanny
J. P. Coullahan, et al., "Field-Reparable Circuit Array", IBM Technical Disclosure, vol. 22, No. 4, 9/1979, pp. 1493-1494.
Kuhn et al., "Proceedings of the Sixteenth Hawaii International Conference on System Sciences 1983", published Jan. 1983, see pp. 215 to 224 Interstitial Fault Tolerance--A Technique for Making Systolic Arrays Fault Tolerant.
Computer, vol. 15, No. 1, Jan. 1982, Snyder, L., "Introduction to the Configurable Highly Parallel Computer", see pp. 47 to 56, especially p. 55.
T. T. Leighton and C. E. Leiserson, "23rd Annual Symposium on Foundations of Computer Science, Chicago, Ill., U.S.A., Nov. 3-5, 1982", published Nov. 1982, see pp. 297 to 311," Wafer Scale Integration of Systolic Arrays.

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