Self-regulating clock generator

Details Self-regulating clock generator Self-regulating clock generator

1990-06-01

1991-10-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307265, 307480, 328 63, H03K 513, H03K 700

Patent

active

050598180

ABSTRACT:
There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.

REFERENCES:
patent: 3454884 (1969-07-01), Ziehm
patent: 4794281 (1988-12-01), Onodera et al.
patent: 4968907 (1990-11-01), Pepper
patent: 4985639 (1991-01-01), Renfrow et al.
patent: 4994687 (1991-02-01), Fuji et al.

Affiliated with

Also associated with

Rating

Self-regulating clock generator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-regulating clock generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-regulating clock generator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-110408