Self regulating body bias generator

Details Self regulating body bias generator Self regulating body bias generator

2002-06-13

2004-05-04

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S281000

Reexamination Certificate

active

06731158

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to controlling the back bias on a functional circuit to reduce power consumption by the functional circuit while maintaining switching speed of the transistors at levels sufficient to satisfy system requirements. More particularly, the present invention relates to biasing a MOS integrated circuit through a closed loop circuit configured to measure a time delay created by a delay circuit, and to generate a back bias voltage dependent on the time delay.
BACKGROUND OF THE INVENTION
Although reduction in power consumption has been an ongoing goal in the field of electronics, the proliferation of portable and space based CMOS devices and microprocessor driven apparatuses has created an ever growing need for power conservation, giving rise to a variety of processes and apparatuses for reducing power consumption within personal computers, including a reduction of power within integrated MOS circuits. Power consumption of a digital circuit equals dynamic power consumption plus static power consumption. This relationship can be represented by the formula:
power≈
fCV
DD
2
+(
V
DD
)(
I
DC
)  1)
where f is the operating frequency, C is the equivalent capacitance of the circuit, and I
DC
is the static current. Because it has long been recognized that dynamic power consumption is proportional to V
DD
2
, it has been similarly understood that a reduction in supply voltage can dramatically reduce power consumption, as illustrated in a paper by von Kaenel, Macken and Degrauwe entitled “A Voltage Reduction Technique for Battery-Operated Systems” in the IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990, pages 1136-1140. A reduction of the supply voltage, however, has the unwanted effect of delaying the switching of the transistors within an integrated circuit, thereby slowing down the critical path of the circuit. If the circuit through-put is slowed below a certain minimum threshold, an integrated circuit can no longer function reliably in the environment for which it was designed.
An alternative approach for reducing power consumption is to raise the threshold voltage of a transistor, typically by a process known as “back biasing” the transistor substrate.
FIG. 1
illustrates an n-channel MOS field effect transistor
100
with a “body bias” or “back bias” voltage
104
applied to the substrate
102
. Increasing the threshold voltage has the desirable effect of decreasing the transistor's leakage current, thereby reducing power consumption. As the threshold voltage is raised, power consumption is reduced, but the switching speed of the transistor is also slowed. Once again, if the switching time of a transistor becomes excessive, the delay will render the circuit inoperative for the environment in which it is intended to function. To maximize the efficiency in terms of power consumption, designs have been proposed wherein the threshold voltage could be raised such that the circuit speed is just fast enough to satisfy system requirements. A fundamental challenge to this design goal is the fact that, although a transistor threshold is typically fixed when the circuit is manufactured, the threshold voltage will typically vary from chip to chip as a result of manufacturing tolerances. More significantly, a circuit degrades over time, typically from heat and radiation. This degradation affects a variety of functional parameters such as the threshold switching voltage and the switching speed of the transistor. Accordingly, if the threshold voltage is set as high as allowable at the time of manufacture to minimize power consumption, as soon as the transistor speed degrades at all, the transistor will be too slow to satisfy system requirements. Alternatively, if the bias is set such that it allows for a certain degradation of switching speed before the transistor falls below the acceptable lower limit, the power consumption is higher than necessary for much of the life of the transistor.
One solution has been to set the body bias as high as allowable, and lower the bias voltage over the life of the transistor as the transistor slows. To achieve this, however, the circuit must include some means of monitoring or estimating the switching speed of the transistors within a circuit to ensure that the speed remains within system requirements. Earlier methods utilizing a back biasing voltage for power reduction have typically used a single reference transistor selected from among the many transistors comprising a MOS integrated circuit. However, if the gradual degradation of the reference transistor did not exactly match the average degradation of the circuit, the technique was inaccurate. Additionally, earlier methods taking advantage of the body bias effect have been component intensive, variously requiring a fixed reference voltage, a fixed reference current, fixed resistors creating a voltage divider for use as a reference voltage, variable frequency clocks, op-amps, and multiple memory registers for storing data defining various voltage levels for application to a back-bias voltage. These various approaches can be seen in a variety of works, including U.S. Pat. No. 3,609,414 to Pleshko et al. entitled “Apparatus for Stabilizing Field Effect Transistor Thresholds,” U.S. Pat. No. 4,142,114 to Green, U.S. Pat. No. 4,670,670 to Shoji, U.S. Pat. No. 5,682,118 to Kaenel et al., U.S. Pat. No. 5,744,996 to Kötzle et al., the above referenced paper by von Kaenel, Macken and Degrauwe, a related paper by Gutnik and Chandraksan entitled “Embedded Power Supply for Low-Power DSP,” and a paper entitled “A Delay Distribution Squeezing Scheme with Speed-Adaptive Threshold-Voltage CMOS (SA-Vt CMOS) for Low Voltage LSIs” by Mizuno and Ishibashi, which was presented at the 1998 International Symposium on Low Power Electronics and Design.
There exists therefore a need for a method and apparatus for reducing the power consumption of a CMOS circuit by controlling the back bias voltage applied to a CMOS circuit. There is a further need for a method and apparatus for reducing the power consumption of a CMOS circuit while monitoring the switching speed of the transistors. There is a further need for a method and apparatus for automatically adjusting the back-bias voltage to insure that the CMOS switching speed does not fall below a certain threshold level. There is also a need for a method and apparatus for controlling the back bias voltage over the life of a circuit that is not dependent on a single reference transistor. There is a further need for a method and apparatus for adjusting a back-bias voltage to reduce power consumption which avoids the addition of excessive ancillary components such as fixed reference voltage sources, fixed current sources, fixed resistors forming voltage dividers for reference voltages, variable speed clocks, op-amps, divide-by-N clock-counters, or multiple memory locations storing data defining various voltage levels for application to a back-bias voltage.
BRIEF SUMMARY OF THE INVENTION
The present invention is a method of and apparatus for reducing the power consumption of a CMOS circuit by controlling the back bias voltage applied to a CMOS circuit. The present invention further provides a method of and apparatus for reducing the power consumption of a CMOS circuit while monitoring the switching speed of the transistors. The present invention further discloses a method of and apparatus for automatically adjusting the back-bias voltage to insure that the CMOS switching speed does not fall below system requirements. The present invention further discloses a method of and apparatus for adjusting a back-bias voltage to reduce power consumption while limiting the addition of excessive ancillary components such as fixed reference voltage sources, fixed current sources, fixed resistors forming voltage dividers for reference voltages, variable speed clocks, op-amps, divide-by-N counters and multiple memory locations for storing data defining various voltage levels for application to a back-bias voltage.
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