Self-planarizing process for shallow trench isolation

Details Self-planarizing process for shallow trench isolation Self-planarizing process for shallow trench isolation

2000-10-12

2003-06-03

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257S510000

Reexamination Certificate

active

06573152

ABSTRACT:

TECHNICAL FIELD
This invention relates to shallow trench isolation, and more particularly to a process for forming shallow trenching isolations and the isolated shallow trenches formed thereby.
BACKGROUND OF THE INVENTION
Shallow trench isolation (STI) is a process for isolating active areas in integrated microelectronic devices. An advantage of using the STI technique rather than the popular local oxidation of silicon (LOCOS) technique is that the latter leaves “field beak” or “bird beak” areas in edges of the insulating dielectric. These areas are generally unusable areas of the integrated circuit and they therefore increase wasted area of the chip. Using the STI technique leaves behind no such artifacts. This advantage of using STI results in a more positive definition of the active areas and therefore reduces overall circuit dimensions.
However, using STI is generally a more complex process than using LOCOS, and therefore generally adds more steps and cost to the process. Defining the isolation regions using STI can be summarized by three major steps, each comprising a more or less extended series of operation and processes.
First, a trench is defined in the silicon substrate. As shown in
FIG. 1
, a starting wafer
5
generally includes a silicon nitride layer
12
and a silicon substrate
10
. The nitride layer
12
can be made from Si
3
N
4
and deposited on the generally planar silicon substrate
10
. An optional PADOX layer
14
is also shown between the substrate
10
and the nitride layer
12
. As shown in
FIG. 2
, trenches
20
are defined in areas which will later be the isolation regions. The silicon substrate
10
is trenched down to a predetermined depth and with a predetermined slope in sidewalls of the trenches.
In the second major step, the trenches
20
are filled with a dielectric material. The trenches
20
thus defined in the silicon substrate
10
are then filled with a dielectric known as the field oxide. This field oxide is typically a silicon oxide. This step of the process is carried out as one or more separate depositions. The deposited dielectrics, if produced by separate depositions, would have different chemo-physical characteristics, and must be made uniform by a later thermal treatment known as densification.
An example of trench
20
filling is shown in FIG.
3
. In that Figure, a first dielectric layer
22
is deposited by HDPCVD into the trenches
20
and onto the other portions of the silicon substrate
10
. The first dielectric layer
22
forms peaked areas over the portions of the silicon nitride layer
12
that remain after the trenches
20
were formed, and causes a generally uneven topology for the wafer
5
. The first dielectric layer
22
must have excellent step coverage in order to completely fill the trenches
20
. Partially or completely unfilled trenches are undesirable because they can interfere with operation of the later-formed circuit. However, filling the trenches with this first dielectric layer deposited by HDPCVD causes the wafer
5
to have a very uneven topology as shown in FIG.
3
. This uneven topology makes it very difficult to later planarize the wafer
5
, which is necessary for further circuit construction. Therefore, this first deposition is followed by a second deposition of a second dielectric layer
24
, such as a TEOS layer formed by LPCVD as shown in FIG.
4
. This TEOS layer
24
is more easily planarized than the first dielectric layer
22
. However, it is impossible for the TEOS layer
24
to be used to fill the trenches
20
of the silicon substrate
10
because of the poor step coverage of the second dielectric layer
24
, and the corresponding problems of partially filled trenches
20
described above. Note too that, during the deposition of the TEOS layer
24
above the first dielectric layer
22
, a thin layer of the TEOS layer
24
is deposited on a backside of the wafer
5
, which will later have to be removed. After the trenches
20
have been filled with the dielectric materials
22
,
24
, the silicon wafer
5
has an uneven topology.
The third major step in an STI process is that the silicon wafer
5
is planarized and active areas are defined. Active areas are first exposed by removing excess deposited dielectric layers
22
,
24
so as to uncover the nitride structures made from the remaining portions of the nitride layer
12
. In order to remove the excess deposited dielectric layers
22
,
24
a Chemical Mechanical Polishing (CMP) technique is generally used. However, in order to utilize CMP, the wafer
5
must be changed from how it appears in FIG.
4
. Primarily, portions of the TEOS layer
24
need to be removed where they correspond with peaks of the first dielectric layer
22
. That will ensure a better planarity of the wafer
5
after the CMP step.
The beginning of the procedure preparing for the CMP step begins by a step of densification to make the two oxide films
22
,
24
more homogeneous, and thus undistinguishable in the CMP process. Once the densification has been completed the procedure continues, shown in
FIG. 5
, with a mask
28
being deposited on the TEOS layer
24
. This mask
28
is sometimes called a counter-mask because it is exactly opposite of the trenches
20
formed in FIG.
2
. Once the mask
28
is completely formed, the TEOS layer
24
is etched down, in areas other than those covered by the mask
28
, to a level nearly even with the top of the highest portions of the first dielectric layer
22
. Forming the mask
28
and etching the TEOS layer
24
are shown in
FIGS. 5 and 6
, respectively.
The mask
28
is then removed, as shown in FIG.
7
. The remaining structure as it is shown in
FIG. 7
is ready for the CMP step or steps. The definition of the shallow trench isolation of the wafer
5
is then completed by partially removing the nitride and optimizing the field height relative to the active areas. After the CMP and definition is complete, the finished structure will look like the one shown in FIG.
8
.
Following the CMP process, the TEOS layer
24
on the backside of the wafer is removed in a step shown in FIG.
9
. Then, the depending on the desired processing, remaining nitride areas
12
and the optional PADOX layer
14
can be removed, leaving the completed STI structures as shown in FIG.
10
.
The critical aspects of such a process scheme as described above are tied to their inherent nature as well as to the large number of the operations involved, which makes it an expensive process for forming isolation regions. Additionally, each step entails changing the fabrication setup, performing measurements, and increases chances for spoilage of the wafer
5
.
Until now, there is no simple, inexpensive way to produce field oxide isolation regions using a shallow trench isolation technique that lessens the problems of the prior art.
SUMMARY OF THE INVENTION
The disclosed process uses a special application of HDPCVD which allows trenches in a silicon substrate to be filled and partially planarized in one step. Thus, presented is a simplified production flow used for implementing shallow trench isolation, whereby the number of the process steps substantially fewer than currently used in the prior art.
Embodiments of the invention provide a method to form isolation structures on a semiconductor substrate. This method begins with forming one or more trenches in the semiconductor substrate and depositing a first portion of a dielectric layer at a first rate by a High Density Plasma—Chemical Vapor Deposition into the trenches and onto the semiconductor substrate. This first deposition at least partially fills the trenches. Next, a second portion of the dielectric layer is deposited at a second rate by the High Density Plasma—Chemical Vapor Deposition over the semiconductor substrate to partially planarize the dielectric layer. This second deposition is preferably performed with a different flow rate of reaction gasses than the first deposition. Finally, a portion of the dielectric layer that was deposited at the second rate is removed.


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