Self-planarized shallow trench isolation

Details Self-planarized shallow trench isolation Self-planarized shallow trench isolation

1999-06-02

2000-12-12

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438221, 438226, 257513, H01L 2176

Patent

active

061598224

ABSTRACT:
A method for implementing self-planarized shallow trench isolation in an integrated circuit. A planarized insulator oxide layer is formed after shallow trench isolation is etched and insulator oxide layer is deposited and etched back. The corners of silicon nitride layer over active area are exposed after the etch back step. Then, a silicon nitride cap layer is deposited. A non-critical photoresist patterning is used to expose the bigger active regions. Afterward, the cap layer on the bigger active regions is removed. Then, the insulator oxide layer under the cap layer is removed by wet etch after stripping of photoresist. Subsequently, wet etch is used to remove the cap layer and the silicon nitride layer. Finally, the self-planarized shallow trench isolation processes are completed after the pad oxide is removed.

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