Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
1999-09-14
2001-11-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
Reexamination Certificate
active
06313479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of nanotechnology. More particularly, the invention relates to systems and methods for fabricating ordered arrays of quantum dots.
2. Discussion of the Related Art
Devices that include quantum dots can be employed as computer components. In the past, three dimensional quantum dots have been formed using a buffer layer on a substrate. The use of such a buffer layer was reported by John Weaver's group at the University of Minnesota in Science (1991) and Physical Review Letters (1998).
However, this previously reported technology results in formation of quantum dots without size ordering. Specifically, the quantum dots have a wide variety of different sizes. Additionally, this technology provides quantum dots without spatial ordering. For instance, the quantum dots are often distributed unevenly across the device.
Heretofore, neither of the requirements of quantum dot size and spatial ordering referred to above has been fully met. What is needed is a solution that addresses at least one or all of these requirements. The invention is directed to meeting these requirements, among others.
SUMMARY OF THE INVENTION
A goal of the invention is to simultaneously satisfy the above-discussed requirements of quantum dot size and space ordering which, in the case of the prior art, are not satisfied.
The invention is a conceptually new approach to fabricating quantum dots. The invention includes the use of charging, and optionally, the use of a buffer layer, the combination being termed buffer layer charging (BLC).
These, and other, goals and embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such modifications.
REFERENCES:
patent: 5888885 (1999-03-01), Xie
patent: 5997958 (1999-12-01), Sato et al.
Weaver, J.H. et al.,Science,vol. 251, “Cluster Assembly of Interfaces: Nanoscale Engineering”, Mar. 22, 1991, pp. 1444-1451.
Huang, Lin et al.,Physical Review Letters,vol. 80, No. 18, Buffer-Layer-Assisted Growth in Nanocrystals: Ag-XE-Si(111), The American Physical Society, May 4, 1998, pp. 4095-4098.
Chey et al. “Interface bonding and manipulation of Ag and Cu nanocrystals on Si(111)-(7×7)-based surfaces” Jun. 1999 Phys Rev B V59 pp16033-16041.
Chang Ming-Che
Pai Woei Wu
Wendelken John F.
Zhang Zhenyu
Chaudhuri Olik
Fulbright & Jaworski
Willie Douglas A.
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