Self-operating PWM amplifier

Amplifiers – Modulator-demodulator-type amplifier

Reexamination Certificate

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Details

C330S20700P, C330S251000

Reexamination Certificate

active

06707337

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to self-running or self-operating PWM (Pulse Width Modulation) amplifiers, and more particularly to a novel self-operating PWM amplifier that can be suitably used to amplify audio signals.
Among examples of the so-called class-D amplifiers are self-running or self-operating PWM amplifiers.
FIG. 11
shows a general setup of a conventional self-operating PWM amplifier. In the figure, the self-operating PWM amplifier includes an integrator circuit that is composed of an operational amplifier
301
and a capacitor
302
connected between an inverted (negative) input terminal and an output terminal of the operational amplifier
301
, a comparator that is composed of resistors R
1
, R
2
and an operational amplifier
303
, a driver
304
, and a CMOS inverter
305
functioning as a switching circuit.
In the CMOS inverter
305
, as illustratively shown in
FIG. 16
, the drains of a PMOS transistor
600
and NMOS transistor
601
are interconnected, and the connection point between these drains is connected to an output terminal
603
. The gates of the PMOS transistor
600
and NMOS transistor
601
are interconnected, and the connection point between these gates is connected to an input terminal
602
. Further, the source of the PMOS transistor
600
is connected to a supply voltage +Vcc, while the source of the NMOS transistor
601
is connected to another supply voltage −Vcc.
The output terminal of the CMOS inverter
305
is coupled, via a low-pass filter composed of an inductance L
1
and capacitor C
1
, to one input terminal of a speaker
306
that is a load of the PWM amplifier, and the other input terminal of the speaker
306
is grounded. In addition, the output terminal of the CMOS inverter
305
is coupled via the resistor R
2
to a noninverted (positive) input terminal of the operational amplifier
303
and also coupled via a feedback resistor R
NF
to a noninverted input terminal of the operational amplifier
301
constituting the integrator circuit.
Output terminal of the operational amplifier
301
of the integrator circuit is coupled via the resistor R
1
to the noninverted input terminal of the operational amplifier
303
of the comparator. Further, a signal source
300
is connected via an input resistor R
IN
to the inverted input terminal of the operational amplifier
301
. Noninverted input terminal of the operational amplifier
301
and inverted input terminal of the operational amplifier
303
are each grounded.
The self-operating PWM amplifier of
FIG. 11
arranged in the above-described manner, as a whole, functions as an inverting amplifier having a gain corresponding to a resistance ratio of R
NF
/R
IN
. Namely, in this self-operating PWM amplifier, a difference between an analog signal (audio signal) V
IN
input from the signal source
300
via the input resistor R
IN
and an output signal (switching signal) negatively fed back from the CMOS inverter
305
via the feedback resistor R
NF
is integrated via the integrator circuit composed of the operational amplifier
301
and capacitor
302
, and the resultant integrated output from the integrator circuit is converted into a binary PWM (Pulse Width Modulated) signal by means of the hysteresis comparator composed of the resistors R
1
, R
2
and operational amplifier
303
.
Further, in the self-operating PWM amplifier, the PWM signal is amplified by the driver circuit
304
, and, on the basis of the PWM signal, the driver circuit
304
drives the CMOS inverter
305
for switching operations. Output from the CMOS inverter
305
is not only supplied to the speaker
306
via the low-pass filter composed of the inductance L
1
and capacitor C
1
but also negatively fed, via the feedback resistor R
NF
, back to the inverted input terminal of the operational amplifier
301
constituting the integrator circuit. In this manner, the PWM amplifier can operate by itself.
When no analog signal V
IN
is input from the signal source
300
to the operational amplifier
301
of the integrator circuit, an output voltage V
3
from the CMOS inverter
305
, functioning as a switching circuit, switches between the level of the supply voltage +Vcc (i.e., “high level”) and the level of the supply voltage −Vcc (i.e., “low level”) with a 50% duty cycle, as denoted by a dot-and-dash line in FIG.
12
.
Because the noninverted input terminal of the integrator-circuit-constituting operational amplifier
301
is fixed to 0 V, when the output voltage V
3
from the CMOS inverter
305
is at the high level, an output voltage V
1
from the operational amplifier
301
of the integrator circuit, integrating the output voltage V
3
from the CMOS inverter
305
, increases in a negative direction (falls) with the passage of time. When the output voltage V
3
from the CMOS inverter
305
has switched to the low level, the output voltage V
1
from the operational amplifier
301
increases in a positive direction (rises). Consequently, the output voltage V
3
from the CMOS inverter
305
presents a triangular voltage waveform as denoted by a broken line in FIG.
12
.
As the output voltage V
1
from the integrator circuit increases in the negative direction (falls), an input voltage V
2
to the noninverted input terminal of the operational amplifier
303
, constituting the hysteresis comparator, also increases in the negative direction. Because the output voltage V
3
from the CMOS inverter
305
, switching to the low level as the input voltage V
2
to the operational amplifier
303
drops to 0 V, is positively fed back to the noninverted input terminal of the operational amplifier
303
via the resistor R
2
. Thus, the input voltage V
2
to the noninverted input terminal of the operational amplifier
303
is rapidly drawn in the negative direction to a level that is determined by the current output voltage V
1
from the integrator circuit, output voltage V
3
from the CMOS inverter
305
and resistance ratio between the resistors R
1
and R
2
.
Then, as the output voltage V
1
from the integrator circuit increases in the positive direction, the input voltage V
2
to the operational amplifier
303
increases. Because the output voltage V
3
from the CMOS inverter
305
, switching to the high level as the input voltage V
2
to the operational amplifier
303
rises to 0 V, is positively fed back to the noninverted input terminal of the operational amplifier
303
via the resistor R
2
. Thus, the input voltage V
2
to the noninverted input terminal of the operational amplifier
303
rapidly rises to a level that is determined by the current output voltage V
1
from the integrator circuit, output voltage V
3
from the CMOS inverter
305
and resistance ratio between the resistors R
1
and R
2
. In this way, the input voltage V
2
to the noninverted input terminal of the operational amplifier
303
varies as denoted by a solid line in FIG.
12
.
When, on the other hand, an analog signal V
IN
is input from the signal source
300
to the operational amplifier
301
constituting the integrator circuit, the capacitor
302
repeats electrical recharging and discharging operations at a rate or with an inclination corresponding to the level of the input signal thereto, so that the output voltage V
1
from the operational amplifier
301
presents a waveform as denoted by a broken line in FIG.
13
. During that time, the CMOS inverter
305
outputs a binary signal, similar to a PWM signal, having pulse widths corresponding to the level of the input analog signal V
IN
(denoted by a solid line in
FIG. 13
) and varying between the high and low levels.
The PWM amplifier generally modulates an input signal with a high-frequency carrier signal, and thus in a case where such amplifiers of two stereophonic channels or more are mounted together on a single semiconductor chip, the amplifiers tend to cause greater mutual interferences therebetween than where liner amplifiers are mounted on the chip. Such great interferences between the amplifiers would often invite crosstalk and beats

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