Self locking dual frequency clock system

Details Self locking dual frequency clock system Self locking dual frequency clock system

1999-04-01

2002-04-16

Gregory, Bernarr E. (Department: 3662)

Communications: directive radio wave systems and devices (e.g.,

With particular circuit

C342S021000, C342S070000, C342S082000, C342S089000, C342S118000, C342S124000, C342S134000, C331S046000

Reexamination Certificate

active

06373428

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to timing circuits, and more particularly to precision swept delay circuits. A particular application is to radar timing circuits, including precision swept delay circuits for equivalent time ranging systems. It can be used to generate a swept-delay clock for sampling-type radar, laser and TDR systems, as well as radio and ultrasonic systems.
2. Description of Related Art
High-resolution pulse-echo systems such as wideband pulsed radar, pulsed laser rangefinders, and time domain reflectometers (TDR) generally sweep a timing circuit across a range of delays. The timing circuit controls a receiver sampling gate such that when an bill echo signal coincides with the temporal location of the sampling gate, a sampled echo signal is obtained. The echo range is then determined from the timing circuit, so highly accurate swept timing is needed to obtain accurate range measurements.
Prior art approaches to swept timing include analog methods and systems: (1) an analog voltage ramp that drives a comparator, with the comparator reference voltage controlling the delay, or (2) a delay locked loop (DLL), wherein the delay between a transmit and receive g clock is measured and controlled with a phase comparator and control loop. Both approaches are subject to component and temperature variations, and are generally limited to an accuracy of 0.01 to 1 percent of full scale. Examples of DLL architectures are disclosed in U.S. Pat. No. 5,563,605, “Precision Digital Pulse Phase Generator” by McEwan, and in copending application, “Phase-Comparator-Less Delay Locked Loop”,filed May 26, 1998, Ser. No. 09/084,541, by McEwan, now U.S. Pat. No. 6,055,287.
A potentially more accurate approach uses two oscillators with frequencies F
T
and F
R
that are offset by a small amount F
T
−F
R
=&Dgr;. In a radar application, a first oscillator of frequency F
T
triggers transmit RF pulses, and a second oscillator of frequency F
R
triggers a short sampling gate for the echo RF pulses. Due to the small frequency difference &Dgr;, the timing of the sampling gate smoothly and linearly slips in phase (i.e., time) relative to the transmit clock such that one full cycle is slipped every 1/&Dgr; seconds. The two frequencies are directly measured and used to control &Dgr;.
The slow phase slip creates a time expansion effect of F
T
/&Dgr; (~100,000 typically). Thanks to the expansion effect, events on a picosecond scale are converted to an easily measurable microsecond scale. In contrast, a real time counter would need a teraHertz clock to measure with picosecond resolution, well beyond present technology.
This two-oscillator technique was used in the 1960's in precision time-interval counters with sub-nanosecond resolution, and appeared in a short-range radar in U.S. Pat. No. 4,132,991, “Method and Apparatus Utilizing Time-Expanded Pulse Sequences for Distance Measurement in a Radar,” issued in 1979 to Wocher et al.
The accuracy of the two-oscillator technique is limited by the accuracy of the clocks, which can be extremely accurate, and by the smoothness, or linearity in phase vs. time, of the phase slip between them. Nothing appears in the prior art to support the linearity of the phase slip—it is not easy to measure, and it is also easy to assume it is somehow perfect. Unfortunately, there are many influences that can affect the smoothness of the phase slip that are addressed by the present invention. These include digital cross-talk that can produce 100 ps of error or more, and offset frequency control circuit aberrations than can introduce even more substantial phase slip nonlinearities.
SUMMARY OF THE INVENTION
The present invention is a precise clock system for pulsed radio, radar, laser, ultrasonic, and TDR ranging systems (and other timing applications which need an offset frequency) requiring high stability and accuracy, and a transmitter-receiver system incorporating the clock system. The clock system generates a first clock signal to drive a transmitter and a second clock signal to drive a sampling-type receiver. The present invention is a two oscillator timing system having a first oscillator to provide the first clock signal and a second oscillator to provide the second clock signal. The frequencies (F
T
, F
R
) of the two clocks differ slightly (by &Dgr;) such that a smooth phase slip occurs between them. Thus, a replica of the echo (travelling at the speed of light for electromagnetic systems) is produced by the sampler on a slow time scale (1/&Dgr;~40 milliseconds), known as equivalent time, which directly allows high resolution (e.g., picosecond) measurements on an expanded scale. In contrast to the prior art, the frequency difference &Dgr; between the two oscillators is not directly measured; instead, an effect arising from &Dgr;—the receive pulse rate—is measured and controlled.
Key advantages to this arrangement include (1) the first oscillator can be totally isolated from the rest of the system (except its connection to a transmitter), so error-producing crosstalk can be eliminated, (2) the first oscillator can be remotely located, such as in a radio system, (3) a simplified implementation can be realized, since a mixer and frequency divider chain is not required, and the overall embodiment is compact and of low cost.
The present invention uses a sampling-type frequency locked loop (FLL) between the receiver and the second clock to accurately control the slip rate &Dgr;, and an optional phase lock port is provided to phase lock &Dgr; to an external reference frequency &Dgr;
REF
. Additionally, the FLL employs a wrong-sideband detector so the FLL can reliably lock to small values of −&Dgr; without a false lock at +&Dgr;, i.e. the FLL will ensure that the second oscillator frequency is slightly lower than F
T
(i.e., F
T
−&Dgr;) rather than slightly higher (i.e., F
T
+&Dgr;).
The present invention differs significantly from prior art timing systems based on offset oscillators in that: (1) the FLL locks to the repetition rate of detected receive pulses, (2) a sample-hold type FLL is used to eliminate phase slip nonlinearities, and (3) there is no direct connection between the transmit clock and the receive clock—offset frequency control is routed through the transmit-receive apparatus.
A primary object of the present invention is to provide a high accuracy swept timing circuit for time-of-flight ranging systems.
Yet another object of the present invention is to provide a simple “plug-and-play” timing system for highly accurate, low-cost ranging systems.
A further object of the present invention is to eliminate errors due to crosstalk and control loop aberrations.
Applications include low cost radars for security alarms, home automation and lighting control, industrial and robotic controls, automatic toilet and faucet control, automatic door openers, fluid level sensing radars, imaging radars, vehicle backup and collision warning radars, and universal object/obstacle detection and ranging. One specific embodiment utilizing the present invention is a time domain reflectometer (TDR) where a pulse is propagated along a conductor or guidewire to reflect from a material for use in a variety of applications, such as an “electronic dipstick” for fluid level sensing.


REFERENCES:
patent: 2245627 (1941-06-01), Varian
patent: 2864956 (1958-12-01), Makow
patent: 3944925 (1976-03-01), De Laune
patent: 4000466 (1976-12-01), Scouten et al.
patent: 4002995 (1977-01-01), Reed
patent: 4042884 (1977-08-01), Querry
patent: 4118673 (1978-10-01), Hafner
patent: 4132991 (1979-01-01), Wocher et al.
patent: 4251777 (1981-02-01), Sartorius et al.
patent: 4322832 (1982-03-01), Sartorius
patent: 4435847 (1984-03-01), Williamson et al.
patent: 4677395 (1987-06-01), Baker
patent: 4974236 (1990-11-01), Gurcan et al.
patent: 5260670 (1993-11-01), Ainsworth et al.
patent: 5343168 (1994-08-01), Guthrie
patent: 5963163 (1999-10-01), Kemkemian et al.
patent: 6072427 (2000-06-01), McEwan

Affiliated with

Also associated with

Rating

Self locking dual frequency clock system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self locking dual frequency clock system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self locking dual frequency clock system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2822717