Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-12-22
2002-04-30
Smith, Matthew (Department: 2825)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S108000
Reexamination Certificate
active
06380772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to circuits to transfer digital signals to a transmission line connecting two integrated circuits. More particularly, this invention relates to circuits that transfer digital signals to an unterminated transmission line while limiting the effects of reflections and noise on power distribution lines.
2. Description of the Related Art
Driver and receiver circuits for the transfer of digital signals between functions of an electronic or computer system are well known in the art. Bus structures such as the Integrated Drive Electronics (IDE) specified in the American National Standards Institute (ANSI) standard X3T10 describe the electrical power and data interface between a computer system board (motherboard) and an integrated disk controller. Generally these driver circuits consist of transistors configured to transfer signals from internal function circuits of the integrated circuit and to condition the signals to be transferred and to transfer the signals to an input/output pad formed at the surface of a semiconductor substrate on which the integrated circuit is formed. Attached to the input/output pad is wirebond. The wirebond is formed of a fine wire connected to the input/output pad at one end and connected to a wire trace that is formed into a bonding pad on a module on which the semiconductor die is mounted at the opposite end of the bonding wire. The wirebond allows the signal further transferred to printed wiring traces on the module. The printed wiring traces of the module are connected to terminal pins of the module. The terminal pins of the module allow the module to be mounted to a printed circuit board (the motherboard or the integrated disk controller). The pins are either connected through vias (holes in the printed circuit board) or in contact with pads formed of printed wiring traces on the surface of the printed circuit board. The pins will be generally soldered to the vias or the contact pads of the printed circuit board. The vias or contact pads are connected to printed wiring traces that conduct the signals from the integrated circuit to other integrated circuits mounted similarly to the printed circuit board. Alternately, the printed wiring traces will be connected to the terminating connector pins of one end of a cable connected to the printed circuit wiring board. The cable has a second terminating connector connected at the opposite end, which is connected to a second printed circuit wiring board. The cable then transfers the signal from the integrated circuit to printed wiring traces on the second printed circuit board. The wiring traces on the second printed circuit wiring board are connected to the vias or bonding pads having the pins of a second integrated circuit module. The pins of the second integrated circuit module are connected through module wiring traces to the module bonding pads. Wirebonds connect the module bonding pads to an input/output pad on a second semiconductor substrate having a second integrated circuit. The input/output pad is connected by interconnecting layers on the surface of the semiconductor substrate to a receiver. The receiver accepts the transferred signal and conditions it for use by the internal circuits of the second integrated circuit.
At lower frequencies, the equivalent circuit of one such signal path to transfer signals between integrated circuit functions on separate printed circuit boards is as shown in FIG.
1
. The output driver is formed of the n-type metal oxide semiconductor (MOS) transistor M
1
and the p-type MOS transistor M
2
. The drains of the n-type MOS transistor M
1
and the p-type MOS transistor M
2
are connected through the I/O signal pad to the load capacitor C
L
. The load capacitor C
L
is composed of the capacitances of the input/output pads on the semiconductor substrate mounted in the second integrated circuit module, wirebond from the input/output pad, the module wiring trace of the second integrated circuit module, module pins of the second integrated circuit module, printed circuit wiring traces of the printed circuit boards, the terminal connectors that attach a cable to the printed circuit boards, the distributed capacitance of the inter-connecting cable, and the input loading capacitance of the receiver.
The source of the n-type MOS transistor M
1
is connected through the parasitic inductance L
Vss
and the pad connector I/O
Vss
to the ground reference potential. The parasitic inductance L
Vss
is the lumped inductance of a wirebond from voltage wirebonding pad of the integrated circuit to the module pin, the module pin itself, and any of the printed circuit wiring traces, connectors, and cabling connecting the ground reference potential to the integrated circuit.
The source of the p-type MOS transistor M
2
is similarly connected through the parasitic inductance L
Vcc
and the pad connector I/O
Vss
to the power supply voltage source V
cc
. The parasitic inductance L
Vcc
is the lumped inductance of the wirebond from the integrated circuit to the module pin of the module containing the integrated circuit, the module pin itself, and any of the printed circuit wiring traces, connectors, and cabling connecting the power supply voltage source to the integrated circuit.
The gates of the n-type MOS transistor M
1
and the p-type MOS transistor M
2
are connected to the internal circuit Int Ckt of the integrated circuit to receive the output signal that is to be transferred to the receiver REC. When the output signal changes from a first voltage level (i.e. 0V) to a second voltage level, (i.e. V
cc
) the n-type MOS transistor M
1
conducts and the p-type MOS transistor M
2
ceases to conduct. Any charge present on the load capacitor CL is conducted through the n-type MOS transistor M
1
to the ground reference potential.
Similarly, when the output signal traverses from the second voltage level (V
cc
) to the first voltage level, the n-type MOS transistor M
1
ceases to conduct and the p-type MOS transistor M
2
conducts. A current is transferred from the power supply voltage source through the p-type MOS transistor M
2
to charge the load capacitor C
L
.
At shorter physical dimensions and at lower frequencies with slower transition times, the schematic of
FIG. 1
is adequate to simulate the performance of the interface. However, as the dimensions increase or the frequency of operation increases, a more accurate model, as shown in
FIG. 2
, must be used. In
FIG. 2
, the drains of the n-type MOS transistor M
1
and the p-type MOS transistor M
2
are connected to the transmission line T
X
through the input/output signal pad. The opposite end of the transmission line T
X
is connected to the load capacitor C
L
. The load capacitor C
L
now represents the lumped capacitance of the terminating pins of the second connector of the cable, the printed circuit wiring traces, the module pins of the second integrated circuit module, the printed wiring traces of the second integrated circuit module, the bonding wire connected to the receiver REC and the input capacitance of the receiver REC itself. The current return lines of the transmission are connected to the ground reference potential.
The transmission line effects of the driver providing or sourcing current or receiving or sinking current from an open circuit produces predictable but undesirable effects to the driver signal placed on the transmission line. The effects or reflections often cause “ringing” or self-oscillation of the driver signal during the transitions between the first voltage level (0V) and the second voltage level (V
cc
).
FIG. 3
shows the addition of a terminating resistor R
T
from the junction of the transmission line T
X
and the receiver to the ground reference potential. In this example, when the output signal V
O
is at the second voltage level, the p-type MOS transistor must remain conducting to keep the input of the receiver at the second voltage level (V
cc
).
It is well known in the art that the terminating resistor R
T
can be placed f
Dinh Paul
Janofsky Eric B.
Marvell International Ltd.
Smith Matthew
LandOfFree
Self-limiting pad driver does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-limiting pad driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-limiting pad driver will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2853247