Self-limiting erase scheme for EEPROM

Details Self-limiting erase scheme for EEPROM Self-limiting erase scheme for EEPROM

1987-04-16

1989-01-10

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365189, 365218, G11C 700, G11C 1140

Patent

active

047978562

ABSTRACT:
A self-limiting scheme to prevent an over-erase condition of a one-transistor EEPROM cell. During an erase cycle, a drain voltage is fed back to a floating gate to counteract a positive erase voltage on the source of the memory cell and therein reduce the electric field across the tunnel oxide leading to the cessation of erase. In another scheme, the drain voltage is fed back to deactivate the erase voltage when a predetermined drain voltage value is exceeded.

REFERENCES:
patent: 4228527 (1980-10-01), Gerber et al.
patent: 4437174 (1984-03-01), Masuoka
patent: 4628487 (1986-12-01), Smayling
patent: 4677590 (1987-06-01), Arakawa

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