Self-latching logic gate for use in programmable logic array cir

Details Self-latching logic gate for use in programmable logic array cir Self-latching logic gate for use in programmable logic array cir

1990-09-13

1992-01-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307445, 307451, 307469, 3072471, 3072721, H03K 1994, G06F 738

Patent

active

050794507

ABSTRACT:
A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided. Each includes first, second and third terminals, with the first terminal of the first transistor being connected to a source of electrical potential, the second terminals of the first and the second transistors being connected to each other to provide a common input terminal for the first and second transistors, the third terminal of the first transistor and the first terminal of the second transistor being connected to the output terminal of the first logic gate, and the third terminal of the second transistor being connected to ground. A second logic gate circuit is provided for including a second logic gate having first and second input terminals, the first input terminal being connected to the output terminal of the first logic gate circuit, the second input terminal providing a latch input terminal for the self-latching gate, and the output terminal of the second logic gate being connected to the common input terminal of the first and second transistors. In a specific embodiment, the present invention provides a NOR gate with a self-latching output, with minimal parts count and power consumption, which is suitable for use in a PAL system. In further more specific embodiments, the invention includes circuitry for verifying the state of the PAL array, circuitry for changing the polarity of the array output and circuitry for providing system security all with minimal parts counts and power consumption.

REFERENCES:
patent: 4124899 (1978-11-01), Birkrer et al.
patent: 4717912 (1988-01-01), Harvey et al.
patent: 4812675 (1989-03-01), Goetting
Monolithic Memories PAL20RA10.

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