Self latching input buffer

Details Self latching input buffer Self latching input buffer

1992-08-17

1994-02-22

Westin, Edward P.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 307480, 307475, G11C 800

Patent

active

052894304

ABSTRACT:
A self latching input buffer is disclosed which includes an address input buffer which is responsive to a first clock signal so as to produce an output signal. data in the input buffer is latched in connection with the receipt of a second clock signal which is produced by a detector which is responsive to the output signal.

REFERENCES:
patent: 4451745 (1984-05-01), Itoh et al.
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 4849935 (1989-07-01), Miyazawa
patent: 4985868 (1991-01-01), Nakano et al.
patent: 5083296 (1992-01-01), Hara et al.
patent: 5144168 (1992-09-01), Tran

Affiliated with

Also associated with

Rating

Self latching input buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self latching input buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self latching input buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-177179