Self latching buffer

Details Self latching buffer Self latching buffer

1977-09-19

1979-03-27

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307270, 307DIG1, 365230, H03K 3286, H03K 3353, G11C 800

Patent

active

041468023

ABSTRACT:
A latching circuit with at least one node which is precharged by a precharge signal and discharged by the latching of a particular state in the latch. The at least one node is fed back to a control electrode of a transistor which is in series with an input terminal of the latching circuit. The feedback from the at least one node controls operation of the series transistor so that an input signal appearing on the input terminal can be locked out when the latching circuit has a desired logic signal latched into it.

REFERENCES:
patent: 3795898 (1974-03-01), Mehta et al.
patent: 3796893 (1974-03-01), Hoffman et al.
patent: 3848237 (1974-11-01), Geilhufe
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3906464 (1975-09-01), Lattin
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4038567 (1977-07-01), Lewis et al.
patent: 4038646 (1977-07-01), Mehta et al.
patent: 4074148 (1978-02-01), Sato
patent: 4077031 (1978-02-01), Kitagawa et al.

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