Self isolation manufacturing method

Details Self isolation manufacturing method Self isolation manufacturing method

1994-12-27

1997-11-11

Fourson, George

Fishing, trapping, and vermin destroying

437 72, H01L 2176

Patent

active

056863470

ABSTRACT:
A method provides for manufacturing an MOSFET semiconductor device with an array of semiconductor structures on a lightly doped semiconductor substrate. A mask is formed upon the substrate with openings therein. An oxide is formed in the semiconductor substrate. The oxide extends down into sunken regions in the substrate through the openings in the mask. The oxide is removed from the substrate opening the sunken regions in the substrate. Spacers are formed in the openings in the mask forming smaller openings in the spacers. Then, ions are introduced into the substrate below the sunken regions through the smaller openings to form channel stop regions. Then the spacers are removed. A second oxide is formed in the sunken regions.

REFERENCES:
patent: 4538343 (1985-09-01), Pollack et al.
patent: 4622096 (1986-11-01), Dic et al.
patent: 5004701 (1991-04-01), Motokawa
patent: 5108937 (1992-04-01), Tsai et al.
Teng C., et al "Optimization of Sidewall Marked Isolation Process", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 1, Feb. 1985.

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