Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2002-09-20
2003-09-23
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S637000, C438S003000, C438S240000, C438S239000, C438S250000, C438S687000
Reexamination Certificate
active
06624040
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods of fabricating a metal-insulator-metal capacitor, and more particularly, to methods of metal-insulator-metal capacitors integrated with copper damascene processes in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. Metal-insulator-metal (MIM) capacitors have been used in the art. However, a number of problems exist. 1) When huge copper plates larger than about 8 to 10 microns are polished using chemical mechanical polishing (CMP), severe dishing occurs. Therefore, big MIM capacitor plates with dimensions greater than 10×10 microns are not possible. 2) Packing density is difficult to increase with passive devices present. A way to overcome this problem in the case of capacitors is to increase the capacitance per unit area. 3) More than one additional mask is required to process a MIM capacitor in the copper backend process. This increases process cost. It is desired to provide a method for forming a MIM capacitor which overcomes these problems.
A number of patents address MIM capacitors. U.S. Pat. No. 6,271,084 to Tu et al shows a MIM capacitor in a dual damascene opening, but copper is not used. U.S. Pat. No. 6,143,601 to Sun shows a tungsten MIM capacitor. U.S. Pat. No. 6,259,128 to Adler et al teaches a copper MIM capacitor that is patterned. U.S. Pat. No. 6,320,244 to Alers et al teaches forming a MIM capacitor in a dual damascene opening where the bottom electrode comprises a barrier metal, but the upper electrode is copper which is planarized using CMP. However, this capacitor takes up both vertical and horizontal space and has limited flexibility in design of the capacitor. U.S. Pat. No. 6,159,787 to Aitken et al show a metal trench capacitor. U.S. Pat. No. 6,025,226 to Gambino et al discloses a MIM capacitor within a trench. However, leakage current may be a problem in this device. U.S. Pat. No. 6,087,261 to Nishikawa et al, U.S. Pat. No. 6,157,793 to Lou, and U.S. Pat. No. 6,069,051 to Nguyen et al disclose MIM capacitors. U.S. Pat. No. 6,117,747 to Shao et al shows a MOM capacitor and a dual damascene process, but the capacitor is not formed completely within a damascene opening.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor.
Another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor having increased capacitance.
Yet another object of the present invention is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process.
A further object is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process wherein erosion and dishing are avoided.
In accordance with the objects of this invention, a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process is achieved. A first dual damascene opening and a pair of second dual damascene openings are provided in a first dielectric layer overlying a substrate. The first and second dual damascene openings are filled with a first copper layer wherein the filled first dual damascene opening forms a logic interconnect and the filled pair of second dual damascene openings forms a pair of capacitor electrodes. The first dielectric layer is etched away between the pair of capacitor electrodes leaving a space between the pair of capacitor electrodes. The space between the pair of capacitor electrodes is filled with a high dielectric constant material to complete fabrication of a vertical MIM capacitor in the fabrication of an integrated circuit device. The fabrication of the capacitor can begin at any metal layer. The process of the invention can be extended to form a parallel capacitor, a series capacitor, stacked capacitors, and so on.
REFERENCES:
patent: 5837578 (1998-11-01), Fan et al.
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6069051 (2000-05-01), Nguyen et al.
patent: 6087261 (2000-07-01), Nishikawa et al.
patent: 6117747 (2000-09-01), Shao et al.
patent: 6143601 (2000-11-01), Sun
patent: 6157793 (2000-12-01), Weaver et al.
patent: 6159787 (2000-12-01), Aitken et al.
patent: 6242315 (2001-06-01), Lin et al.
patent: 6259128 (2001-07-01), Adler et al.
patent: 6271084 (2001-08-01), Tu et al.
patent: 6271555 (2001-08-01), Hakey et al.
patent: 6320244 (2001-11-01), Alers et al.
patent: 6346454 (2002-02-01), Sung et al.
patent: 6399495 (2002-06-01), Tseng et al.
patent: 6426249 (2002-07-01), Geffken et al.
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Ho Chaw Sing
Martin John E.
Ng Chit Hwei
Chartered Semiconductor Manufacturing Ltd.
Everhart Caridad
Luu Chuong A
Pike Rosemary L.S.
Saile George O.
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