Self-initialized soft start for Miller compensated regulators

Details Self-initialized soft start for Miller compensated regulators Self-initialized soft start for Miller compensated regulators

2002-04-01

2003-09-09

Berhane, Adolf D. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S280000

Reexamination Certificate

active

06617833

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to voltage regulators, and more particularly relates to methods for preventing overshoot in Miller compensated voltage regulators during enable.
BACKGROUND OF THE INVENTION
Electronic circuits are increasingly used in portable and mobile applications in which low power consumption is highly desirable in order to avoid the necessity of large and bulky battery supplies. Such applications include wireless phones, personal pagers, personal digital assistants, etc.
One way of achieving such low power consumption is to provide a so-called Disable, or, Power Down, mode for the electronic circuit. Disable mode is provided as a general matter by including a module that monitors the use of the circuit and that signals the circuit to change from a normal mode to a disable mode when the circuit has not been called upon for use after a predetermined time period. This is frequently done by deactivating an enable signal for the circuit. In response, the circuit changes to a disabled state so that it consumes zero or the minimum power possible. When the module detects that the circuit is required for use again, the module signals the circuit to return to normal mode by reactivating the enable signal.
One circuit that finds frequent use in such applications is the Miller compensated voltage regulator. Such voltage regulators are considered desirable due to their flexible requirement regarding external filter capacitors. However, a problem arises in such regulators during the transition from disabled mode to enabled mode. This can be understood by reference to
FIG. 1
, which shows a circuit diagram of a prior art Miller compensated voltage regulator with enable/disable capability. Briefly, in the circuit of
FIG. 1
, an input differential pair of PMOS transistors MP
1
and MP
2
has current provided to their sources by current source
12
sourcing current I
TAIL
. Their drains are connected to a current mirror comprising NMOS transistors MN
1
and MN
2
. A voltage reference V
REF
, such as a bandgap voltage, is provided to the gate of transistor MP
2
, while a feedback voltage V
FB
developed at the connection node FB of resistors R
1
and R
2
, connected in series between the output node and ground, is provided to the gate of transistor MP
1
. The resulting voltage at the connection node between the drain of transistor MP
2
and MN
2
, node N
CC
, is provided to the non-inverting input of an amplifier A
2
, which has a bias voltage V
BIAS
provided to its inverting input to control the magnitude of the output voltage V
OUT
at the output node OUT. The output of amplifier A
2
controls the gate of a pass PMOS transistor MP
3
connected between the power supply V
DD
and the output node. A filter capacitor C
F
, with its equivalent series resistance R
F
, is connected in parallel with a load, between the output node and ground. Miller compensation is provided by compensation capacitor C
C
connected between node OUT and node N
CC
.
Control of standby versus normal mode is provided by NMOS transistor MN
3
connected by its source and drain between the source and drain, respectively, of transistor MN
1
, NMOS transistor MN
4
connected by its source and drain between the source and drain, respectively, of transistor MN
2
, and by PMOS transistor MP
4
connected by its source and drain between the source and gate, respectively, of transistor MP
3
. The inverse of the enable signal, {overscore (ENB)}, is provided to the gate of transistors MN
3
and MN
4
, while the enable signal, ENB, is provided to the gate of transistor MP
4
. When ENB is low, and thus {overscore (ENB)} is high, the circuit is disabled. In this state, transistor MN
3
turns off transistors MN
1
and MN
2
by shorting their gates to ground, transistor MN
4
pulls node N
CC
to ground, and transistor MP
4
turns off transistor MP
3
and amplifier A
2
. Thus, the regulator circuit consumes, essentially, zero current. In addition, both nodes OUT and FB are grounded by resistors R
1
and R
2
.
During the transition from disable to enable, when ENB is being brought high and {overscore (ENB)} is being brought low, transistors MN
3
, MN
4
and MP
4
are all being turned off, and amplifier A
2
is being enabled. Due to the fact that the gate of transistor MP
1
is already grounded by node V
FB
, all of the current I
TAIL
flows through transistors MP
1
and MN
1
. Since transistors MN
1
and MN
2
are connected as a current mirror, this current through transistor MN
1
is mirrored into transistor MN
2
, causing node N
CC
to be fully discharged by the current I
MN2
through transistor MN
2
. As this occurs, amplifier A
2
is overdriven and turns the pass device MP
3
fully on, which pumps current I
CF
into the filter capacitor C
F
, as well as current I
CC
into compensation capacitor C
C
. The current I
CF
through C
F
determines the slew rate of the regulator output V
OUT
. The discharging current I
MN2
, along with capacitor C
C
, determines the slew rate of node N
CC
. Given the fact that V
OUT
is ramping up, N
CC
still ramps up, but at a slower slope due to the discharging current I
MN2
. Depending on the difference between these two rates, if by the time V
OUT
reaches the desired output level, V
REG
, but the voltage V
NCC
at node N
CC
is still lower than V
BIAS
, which means that amplifier A
2
is still overdriven at the negative input, then V
OUT
will still keep rising until V
NCC
reaches V
BIAS
and shuts off the pass device transistor MP
3
. However, by then overshoot has already occurred, and the delay of the circuit response only makes it even worse. As a result, V
NCC
will go much higher than V
BIAS
, and the regulator will not settle back into its linear region until node OUT is discharged sufficiently so that V
OUT
has settled to the desired output level V
REG
.
This is shown in
FIG. 4
, which is a graph of voltage versus time, showing V
OUT
and V
NCC
, with the transition to enable beginning at time equal zero. As shown, at time t
1
V
OUT
has reached V
REG
, as shown at
41
, but V
NCC
, as shown at
42
, is still below V
BIAS
. As a result, V
OUT
continues to rise above V
REG
until, at time t
2
V
NCC
reaches V
BIAS
, as shown at
43
. However, V
NCC
continues above V
BIAS
, since V
OUT
is above V
REG
. Eventually, however, both V
OUT
and V
NCC
settle toward their steady state voltages, V
REG
and V
BIAS
, respectively. Throughout the enable process, as described above, the desirable linear slew characteristic of the Miller effect never occurs, because amplifier A
2
always saturates in either direction, the root reason being that Node N
CC
ramps up too slowly relative to node V
OUT
.
It would therefore be desirable to have a Miller compensated voltage regulator with enable/disable capability that avoids the problems described above.
SUMMARY OF THE INVENTION
As a general matter, the invention provides protection against overshoot as described above. This is done by controlling the initialization of an internal connection node of a Miller compensation capacitor so as to ensure that the Miller effect provides a linear slew rate at the output node. The rate of increase of the voltage at the internal node is controlled to as to rise to the level of a bias voltage, or to nearly the level of the bias voltage, before the output node reaches the desired output level.
According the invention there is provided a Miller compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port. The voltage regulation circuit includes a first amplifier adapted to receive a reference voltage at a first input, having a second input, and having an output, and also a second amplifier having a first input coupled to an internal node, the internal node being coupled to the output of the first amplifier, the second amplifier having a second inpu

Affiliated with

Also associated with

Rating

Self-initialized soft start for Miller compensated regulators does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-initialized soft start for Miller compensated regulators, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-initialized soft start for Miller compensated regulators will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3062540