Self-enabling latch

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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327 73, 327198, 327211, 327225, H03K 3037, H03K 3356

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active

056401159

ABSTRACT:
A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.

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Morteza Afghahi, "A Unified Single-Phase Clocking Scheme for VLSI Systems", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 225-233.

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