Self driven active clamp

Details Self driven active clamp Self driven active clamp

2001-08-27

2002-09-17

Nguyen, Matthew (Department: 2838)

Electric power conversion systems

Current conversion

Including d.c.-a.c.-d.c. converter

C363S021040

Reexamination Certificate

active

06452818

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to switching-type power converters and in particular forward and flyback-type converters that have synchronous output rectifiers. Converters with self-synchronized rectifiers refer to MOSFET devices used as rectifiers. The gates of these devices are driven by the secondary voltage signal of the power transformer. The use of so-called self-driven synchronous rectifiers in buck-driven converters is limited by the inefficiency of these rectifiers. The reset voltage for the transformer core in forward converters de-signed without an active clamp limits the conduction time of one of the MOSFETs in the synchronous rectifiers, thus pre-venting the converter from operating at maximum efficiency.
BACKGROUND OF THE INVENTION
In the converter shown in
FIG. 1A
, a conventional for-ward topology of the prior art with an isolating power trans-former is combined with a self-synchronized synchronous rectifier. In such a rectifier, controlled devices are used with the control terminals (gates) being driven by the secondary winding of the power transformers.
A DC input voltage, V
IN
, at input
100
, is connected to the primary winding
106
of the power transformer by a MOSFET power switch Q
1
104
. The secondary winding
108
is connected to an output lead
118
through an output filter inductor
114
and a synchronous rectifier including the MOSFET rec-tifier devices Q
2
110
and Q
3
112
. Each rectifying device includes a (parasitic) body diode
120
and
122
respectively.
With the power switch Q
1
104
conducting, the input volt-age is applied across the primary winding
106
. The second-ary winding
108
is oriented in polarity to the primary voltage with a current flow through the inductor
114
, the load is connected to the output lead
118
and back through the MOSFET rectifier Q
2
110
to the secondary winding
108
.
The current path provided by the conduction of the MOSFET rectifier Q
3
112
maintains continuity of the cur-rent flow in the inductor
114
. An output filter capacitor
116
shunts the output of the converter.
The gate drive signals for the MOSFET rectifiers are pro-vided by the voltage appearing across the secondary winding
108
.
In
FIG. 1B
, the voltage and current waveforms of the converter from
FIG. 1A
are shown graphically. Referring to
FIG. 1B
, as the pulse width modulator (PWM)
102
, turn off MOSFET
104
disconnecting the primary winding
106
of the power transformer.
The drain voltage of Q
1
140
rises and due to parasitic capacitance of the input and output, assumes a sinusoidal wave-form from t
0
to t
1
. During this period, t
0
-t
1
, the power transformer core resets itself (reset period). The top or sinusoidal portion of
140
appears as the drain voltage of Q
2
and the gate of Q
3
shown as VDQ
2
/VGQ
3
in
142
. During the reset period, t
0
-t
1
, IQ
2
146
drops to zero and all the current through the inductor
114
is supplied by Q
3
shown in
148
. Specifically IQ
3
148
assumes its maximum at t
0
and then linearly decreases from t
0
to t
1
. From t
1
to t
2
, both MOSFET rectifiers Q
2
and Q
3
are off because the gate driving signals of both Q
2
144
and Q
3
142
are zero. The period from t
1
to t
2
is a so-called “dead time” period in which no power transfer or core resetting takes place in the power transformer.
At t
1
(t) to t
2
, the inductor current shown in
150
continues to flow through the body diodes of Q
3
122
and Q
2
120
. Most of the inductor current flows through
122
and a small portion through
120
due to the fact that the secondary winding of the power transformer is in series with diode
120
. The forward voltage drop of the MOSFET body diodes is close to 1 volt, which is very high when compared to 0.1 volts when the MOSFET is on.
The dead time period, t
1
-t
2
, increases with increasing in-put voltage line V
IN
. This large increase of the dead time, which assumes its maximum value at maximum input volt-age V
IN
, results in the synchronous rectifier of
FIG. 1
offering its worst efficiency at maximum input voltage.
At t
2
the gate voltage of Q
2
110
is zero, the secondary momentarily forward biases the body diode
120
of Q
2
110
allowing the secondary current to flow. As soon as the dotted end of secondary
108
exceeds the gate threshold voltage of Q
2
110
, the body diode is short circuited by the channel of Q
2
110
allowing all the secondary current to go through the channel.
From t
2
to t
3
, Q
1
104
turns on again (the power transfer period of the conversion cycle) and Q
2
110
turns on connecting the secondary
108
of T
1
through inductor
114
to the output terminal
118
.
During t
2
-t
3
, energy is stored at the output inductor
114
, the charge is restored at output capacitor
116
and all the load current is carried through Q
2
110
. The gate driving signal for Q
2
110
is shown in
144
, which is the inverted lower part of the drain waveform of Q
1
140
. The synchronous rectifiers driven directly from the secondary of the forward converter shown in
FIG. 1A
prohibit the converter from achieving maximum possible efficiency due to the operating nature of the unclaimed forward converter.
Even though the self-driven synchronous rectifiers in the forward converter are simple and low-cost, the inherent low efficiency reduces the maximum possible power density and the converter's reliability making the converter unsuitable for high-power density. (Therefore there is a need for an improved version of a forward unclamped converter with synchronous rectifiers.)
Forward converter designs utilizing an “active clamp” to clamp the primary voltage generated during the reset period of the transformer core, when the converter must operate over more than 2:1 input voltage range, at high input voltage also enter into a dead time period.
Forward converters with an active clamp require more complex timing circuitry and additional power MOSFETs. Also, as it is pointed above when the converter operates over a wide input range, the self-driven synchronous rectifiers will encounter a dead time period.
An active clamp circuit is described by Vicor Corporation in its U.S. Pat. No. 4,441,146.
SUMMARY OF THE INVENTION
This invention combines a storage capacitor and control circuitry for charging and discharging the storage capacitor. The capacitor provides energy that switches or resets a transformer winding of a forward DC/DC converter. The drive signals for the control circuitry are taken from transformer windings. In virtually all DC/DC converters, a pulse width modulator signal drives an FET switch in the primary of a transformer. When that FET switch is turned OFF, the drain of the FET, and transformer connection to that primary switch, rises and through drive circuitry turns stores magnetic energy from the transformer in the storage capacitor. After the capacitor has reached its highest level the capacitor will start to discharge through a path provided, and thereby turns on a solid state switch that further discharges the storage capacitor through the transformer thereby resetting the transformer core. When the primary switch turns back ON, the solid state switch is turned OFF via the drive circuit and the capacitor is further discharged.
Bipolar or N, or P type FET transistors may be used in the control circuitry, as is known in the art.
The solid state switch is turned ON after the switch in the primary is turned OFF, and the solid state switch is turned OFF after the primary switch is turned ON.


REFERENCES:
patent: 4441146 (1984-04-01), Vinciarelli
patent: 5726869 (1998-03-01), Yamashita et al.
patent: 5734563 (1998-03-01), Shinada
patent: 6278621 (2001-08-01), Xia et al.
patent: 6288920 (2001-09-01), Jacobs et al.
patent: 6304463 (2001-10-01), Krugly

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