Self-disabling power-up detection circuit

Details Self-disabling power-up detection circuit Self-disabling power-up detection circuit

1993-04-14

1994-06-21

Wambach, Margaret Rose

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072964, 3072965, 307264, H03K 301

Patent

active

053230671

ABSTRACT:
A CMOS power-up reset circuit provides a power-up output signal, useful to external circuits, when an applied power supply voltage exceeds a first predetermined value, and includes a ratioed transistor divider to generate a voltage on a sensing node which is a portion of the power supply voltage during a power-up transient. The circuit regeneratively latches when the rising power supply voltage and the sensing node voltage differ by more than a second predetermined value, such as a P-channel threshold voltage. A feedback signal subsequently disables current flow through the power-up reset circuit to virtually eliminate static power dissipation, and the power-up output signal is generated. Circuit provisions are incorporated to prevent capacitive coupling from the rising power supply voltage, through the N-wells of the P-channel transistors, to critical internal circuit nodes. The first predetermined value of the applied power supply voltage at which the circuit provides a power-up output signal is configurable by adjusting the ratio of two P-channel transistors.

REFERENCES:
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patent: 4558233 (1985-12-01), Nakamori
patent: 4633107 (1986-12-01), Norsworthy
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patent: 4970408 (1990-11-01), Hanke et al.
patent: 5051611 (1991-09-01), Kantz
patent: 5111067 (1992-05-01), Wong et al.
patent: 5136181 (1992-08-01), Yukawa
patent: 5159206 (1992-10-01), Tsay et al.
United States SIR, Piasecki, Registration No. H497, Published Jul. 5, 1988.

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