1993-03-31
1997-09-30
Sheikh, Ayaz R.
395382, 395391, G06F 900, G06F 1500
Patent
active
056734093
ABSTRACT:
A method and apparatus for defining, in a computing system, the bit size of an instruction to be executed by a processing unit. Instructions are realized in the form of a plurality of memory location devices. At least one of said memory location devices, in a predetermined position, is established as a MODE bit. The MODE bit assumes a first value indicative of parallel instruction execution and assumes a second value indicative of non-parallel instruction execution.
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Alexander Thomas
Hicok Gary Dwayne
Kim Yongmin
Lim Yong Je
Moy Jeffrey D.
Sheikh Ayaz R.
VLSI Technology Inc.
Weiss Harry M.
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