Self correcting single event upset (SEU) hardened CMOS register

Details Self correcting single event upset (SEU) hardened CMOS register Self correcting single event upset (SEU) hardened CMOS register

1987-08-20

1988-11-15

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 377 30, 377 79, H03K 3037, H03K 3356

Patent

active

047852003

ABSTRACT:
A self correcting single event upset-hardened CMOS register comprises a master portion and a slave portion. The master portion is coupled to a source of data and includes a feedback means such that said master portion can store said data during the first phase of a bi-phase clock signal. A slave portion including a second feedback path, has an input coupled to the output of said master portion and has an output which comprises the output of the register. An odd plurality of inverters is placed in series in the feedback path so as to isolate each node which is a possible site for high-energy particle impingement from other nodes in the loop and to attenuate and delay any resulting impulses such that the state of the error pulse cannot be maintained thus permitting the slave loop to remain in the state determined by the preceding data pulse.

REFERENCES:
patent: 4199810 (1980-04-01), Gunckel, II et al.
patent: 4394769 (1983-07-01), Lull
patent: 4399377 (1983-08-01), Jones

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