Self correcting data re-timing circuit and method

Details Self correcting data re-timing circuit and method Self correcting data re-timing circuit and method

2007-12-11

2007-12-11

Lugo, David B. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S376000

Reexamination Certificate

active

10373301

ABSTRACT:
An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.

REFERENCES:
patent: 6801592 (2004-10-01), Christensen
Intel® LXT16713 and LXT16714; downloaded from http://www.intel.com/design
etwork/products/optical/PHYs/1xt16713-14.htm on Feb. 18, 2002; pp. 1 to 6.
Zhong, Huiqing; Long, Stephen I.; Monothic Clock and Data Recovery Chip for 10GB/S Fiber Communications Systems; Final Report 1997-98, Mirco Project #97-105 Industrial Sponsor: Conexant Systems, Inc.; pp. 1-4.

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