Static information storage and retrieval – Floating gate – Particular biasing
Utility Patent
1999-10-28
2001-01-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185330
Utility Patent
active
06169693
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to flash memory cells, and more specifically to a novel method of erasing flash memory cells.
A flash memory is a specific type of nonvolatile memory. Specifically, a flash memory comprises a plurality of EEPROM (electrically erasable programmable read-only memory) cells which are bitwise or bytewise programmable to any combination of data values, but are erased as a group, hence the term “flash” memory. Each group of cells which can be erased separately from other groups of cells is referred to as a “sector” of the flash memory. A flash memory can have one or more sectors. In a typical embodiment of the simplest flash memory cell, a cell comprises a single transistor with a control gate, a source and a drain. The source and drain are embedded in a substrate separated by a channel. The control gate overlies at least a part of the channel region and is electrically insulated therefrom, typically by an oxide layer.
When certain voltages are applied to the source, drain and control gate, current can be made to flow between the source and drain through the channel. In the typical flash memory cell, a floating gate is interposed between at least a part of the channel and at least a part of the control gate, insulated each of those components. Since the floating gate is isolated from the other components, it tends to retain a charge placed thereon, and therefore, by associating particular amounts of charge with particular stored values, bits of information can be stored in the cell by varying the amount of charge on the floating gate.
By convention, adding charge to (subtracting electrons from) the floating gate is referred to as “programming” the cell, while the opposite is referred to as “erasing” the cell. Additional details of conventional flash memory devices are shown in U.S. Pat. Nos. 4,698,787, 5,077,691, 5,313,086 and 5,521,886, each of which is incorporated by reference herein for all purposes.
A memory cell is read by biasing the cell and measuring the current through the cell. The voltage, Vt, at which the cell saturates affects how much current passes through the cell, and therefore is an important indicator of contents of the cell, as is well known in the art of flash memories. Preferably, Vt is a positive voltage, because otherwise the cell would turn on even in the absence of an applied control gate voltage. A condition where the threshold voltage Vt is negative is referred to as an “over-erase” condition. Because an over-erased cell would turn on even in the absence of a control voltage, the over-erase condition is to be avoided.
Several approaches to avoiding over-erased cells have been in use. One method of avoiding over-erase is referred to as hot carrier injection during source disturb. Details of this method can be found in S. Yamada, “A Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injection”,
IEEE Trans. Electron Devices,
vol. 43, pp. 1937-1941, November 1996, which is incorporated by reference herein for all purposes. With this approach, the control gate, drain and substrate are grounded while the source is biased at 6.5V. At these biases, a weak hot carrier injection will be created because a lateral field will exist and the floating gate charge will be at a different potential than the substrate (either holes or electrons will flow to the floating gate, depending on its potential). The hot carriers are injected into the floating gate, and with the reinsertion of charge onto the floating gate, threshold voltage will rise to a stable threshold voltage above ground potential. While this method may be used to raise the threshold voltage above the ground potential, it requires extra design work and increases the probability for error as additional circuitry is required to control this over-erase correction process. Additionally, the above-described process lengthens the time needed to erase a cell by as much as 100 ms (milliseconds). Furthermore, additional time and circuitry are needed to verify whether over-erased cells have been corrected.
An additional disadvantage of this method is that if the hot carrier injection takes place near the drain, oxide trap-up and interface generation cause serious read current degradation, thereby shortening the endurance margin. If the hot carrier injection takes place at the source, the adverse effects are not as great. Nevertheless, it is inefficient to try hot carrier injection when the control gate is grounded, because a strong vertical field would not be present to assist the carriers through the oxide.
Some of the above disadvantages may be overcome by using Fowler-Nordheim (FN) tunneling. With this approach, the source and drain are grounded, the control gate is set to a positive voltage and the substrate is set to a negative voltage. This method also has the disadvantage of requiring time, design effort, and chip real estate. An example of this process is described as a two-step erasing scheme described in K. Oyama, et al., “A Novel Erasing Technology for 3.3V Flash Memory With 64 Mb Capacity and Beyond,”
IEDM Tech. Dig.,
1992, pp. 607-610, which is incorporated herein by reference for all purposes. As described there, the second step of the two-step process can add as much as looms to an erase step.
From the above, it is seen that an improved method of correcting for over-erase is needed.
SUMMARY OF THE INVENTION
In one embodiment of an over-erase method according to the present invention for performing a self-converging erase on a flash memory cell a bias on a control gate is rapidly switched while a lateral field is present in the cell's channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and preferably the change in bias of the control gate is sufficiently fast to provoke a transient response at the floating gate. The net transient vertical field formed across the tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection from the channel region to the floating gate.
In a specific embodiment, the control gate bias falls from a negative voltage to zero, inducing a positive transient response on the floating gate, and thus the hot carrier injection is electron injection to the floating gate. This method is self-converging, since carrier injection onto the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the erase step. Since the bulk of the self-converging effect occurs immediately after the control gate voltage transitions and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.
One advantage of this erase process is that it requires no substantial extra procedures to correct for over-erase, which simplifies circuit design.
Another advantage of the erase process is increased reliability. Since hot carrier injection takes place at the source side, it has an insignificant effect on the read current. Also, with the vertical field assisting the hot carrier injection process, injection is very efficient and requires less time.
A further understanding of the nature and advantages of the invention herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 5357476 (1994-10-01), Kuo et al.
patent: 5406524 (1995-04-01), Kawamura et al.
patent: 5491657 (1996-02-01), Haddad et al.
patent: 5687118 (1997-11-01), Chang
patent: 5751631 (1998-05-01), Liu et al.
patent: 5790460 (1998-08-01), Chen et al.
S. Yamada, et al., “A Self-convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM,”IEDM Tech. Dig., 1991, pp. 11.4.1-11.4.4.
K. Oyama, et al., “A Novel Erasing Technology for 3.3V Flash Memory with 64Mb Capacity and Beyond,”IEDM Tech. Dig.1992, pp. 607-610.
P.Pavan, et al., “Flash Memory Cells—An Overview,”Proceedings of the IEEE, vol. 85, No. 8, (Aug. 1987) pp. 1248-1271.
Chan I-Chuin Peter
Qian Feng Frank
Wang Hsingya Arthur
Auduong Gene N.
Hyundai Electronics America Inc.
Nelms David
Townsend and Townsend / and Crew LLP
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