Self-controlled output stage with low power bouncing

Details Self-controlled output stage with low power bouncing Self-controlled output stage with low power bouncing

1992-08-05

1994-05-24

Cross, E. Rollins

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307572, 307443, H03B 104, H03K 1716

Patent

active

053151879

ABSTRACT:
An output stage that reduces power or ground bouncing caused by a capacitive load while either a single or multiple outputs are switching at the same time. A first control means coupled to a power source generates first control signal to the gate terminal of a first MOS transistor in response to an input signal. A second control means coupled to ground generates a second control signal to the gate terminal of the second MOS transistor in response to the input signal. A first gate control means generates third and fourth control signals to the gate terminals of the first and second MOS transistor respectively, in response to the input signal, to turn on one of the first and second MOS transistors partially. A second gate control means generates fifth and sixth control signals to the gate terminals of the first and second MOS transistor respectively, in response to the input signal and the output signal, to turn on said one of the first and second MOS transistors entirely.

REFERENCES:
patent: 4329600 (1982-05-01), Stewart
patent: 4567378 (1986-01-01), Raver
patent: 4612466 (1986-09-01), Stewart
patent: 4862018 (1989-08-01), Taylor et al.
patent: 4961010 (1990-10-01), Davis
patent: 5111076 (1992-05-01), Tarng
patent: 5138194 (1992-08-01), Yoeli

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