Self-configuring modular computer system with automatic address

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34082507, 34082508, 34082552, G06F 1516, G06F 1322

Patent

active

047274751

ABSTRACT:
An initial polling sequence for configuring a modular computer system employing a system bus for interconnecting the CPU and various modules attached to the bus. At the beginning of the polling sequence, a bus base address register in each module is preset to a port 0 address by the CPU. A POLL signal is generated by the CPU and intercepted by the closest module, which responds by placing a module identification character on the data lines of the system bus. The CPU receives the module identification character, stores this character in a table and issues a bus base address for that module. Upon receipt of the bus base address, the module presently active in the polling sequence issues a POLL command to the next module on the system bus. The poll sequence is repeated until all modules have been assigned and have received a bus base address.

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patent: 4281392 (1981-07-01), Grants et al.
patent: 4360870 (1982-11-01), McVey
patent: 4468729 (1984-08-01), Schwartz
patent: 4562535 (1985-12-01), Vincent et al.
patent: 4622633 (1986-11-01), Ceccon et al.

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