Self-configurable computer and memory system

Details Self-configurable computer and memory system Self-configurable computer and memory system

1979-07-12

1982-06-01

Shaw, Gareth D.

Boots, shoes, and leggings

324 73AT, 324 73PC, G06F 1104

Patent

active

043331424

ABSTRACT:
Computer and memory system on a wafer which contains redundant elements and which is capable of self-testing and self-configuration to form a complete system consisting of a central processing unit (CPU), a read only memory unit (ROM), and a plurality of read/write random access memory units (RAM). These units are interconnected by a common bus, which is also available for external connections to the wafer. The first CPU tests each ROM to find a good one and then uses the program contained in that ROM to test itself. If the first CPU does not test satisfactorily, the remaining CPU's are tested until a good one is found. The RAM's are then tested with the good ROM and CPU, and the results are tabulated to form a page oriented computer system.

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patent: 4058851 (1977-11-01), Schevneman
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