Self-configurable circuit structure for achieving wafer scale in

Communications: electrical – Digital comparator systems

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324 73PC, 364900, G11C 1140

Patent

active

040386481

ABSTRACT:
A self-configurable circuit structure and method for forming the same, for achieving wafer scale integration including the combination of an integrated circuit wafer having an input and an output, wafer control means to provide test and operational modes, at least one unit circuit on the wafer connected to the wafer control means, coupled between the wafer input and output. The unit circuit includes a semi-conductor chip, test means for functional testing of the chip and circuit control means responsive to the output of the test means to intercouple the unit circuit if it is properly functioning between the wafer input and output to form a functional circuit.

REFERENCES:
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patent: 3234521 (1966-02-01), Weisbecker
patent: 3434116 (1969-03-01), Anacker
patent: 3478286 (1969-11-01), Dervan
patent: 3714637 (1973-01-01), Beausoleil
patent: 3803562 (1974-04-01), Hunter
patent: 3810301 (1974-05-01), Cook
patent: 3882470 (1975-05-01), Hunter
patent: 3900837 (1975-08-01), Hunter

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