Self-compensating phase detector

Details Self-compensating phase detector Self-compensating phase detector

2001-02-13

2003-02-11

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S163000, C375S375000, C375S376000, C331S012000, C331S025000

Reexamination Certificate

active

06518806

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to clock signaling. More specifically, the invention relates to synchronization of an internal clock signal with a reference clock signal.
2. Related Art
The goal of a phase lock loop (PLL) is to synchronize otherwise asynchronous clock signals. To accomplish this synchronization, the PLL uses a phase detector which compares the phase of the two clocks that are to be synchronized and indicates the distance from synchronization. Ideally, if both clock signals are synchronized the output of this phase detector is zero. If the first signal is too fast the output is positive and if the first signal is too slow the output is negative. In reality due to physical limitations in design such as path mismatch and/or device mismatches a static phase error usually exists. This means that the phase detector will output zero when a static phase difference exists.
FIG. 1
is block diagram of a prior art phase lock loop. A reference clock signal (REF_CLK)
1
is input to phase detector
10
. A second input of phase detector
10
is a clock signal (CLK)
2
generated from voltage controlled oscillator
12
. Phase detector
10
compares the phase of the REF_CLK
1
to the phase of CLK
2
. The result of the comparison is filtered by filter
11
. The output of the filter drives the voltage controlled oscillator (VCO)
12
possibly through an amplifier (not shown) to generate the CLK
2
. When the above discussed static phase error exists, the CLK
2
generated by VCO
12
will not be exactly synchronized with the REF_CLK
1
. This results in non-ideal timing constraints in PLL applications and poor Bit Error Rates (BERs) in clock recovery circuit (CRC) applications.
The problem of static error is exacerbated as the frequency of REF_CLK increases. For a REF_CLK at two gigahertz (0.5 nanosecond period), even slight variations in delay through critical circuits can result in extreme deviations from the ideal sampling point. For example, a 63 pico second delay is equal to a 45° phase error at two gigahertz. In a data transfer system where a stream of random data is to be synchronized with a clock used to sample the data, the phase lock loop must lock the VCO clock signal to within a 10° phase difference to minimize the effect of phase difference on the BER. Prior art phase detectors cannot deliver this performance reliably under the variations in environment the phase detector is likely to encounter in actual use.
In view of the foregoing, it would be desirable to have a method and apparatus that reliably matches the phase of a reference clock to a second clock signal even at very high clock rates.
BRIEF SUMMARY OF THE INVENTION
An apparatus for compensating for phase error is disclosed. A first phase detector is replicated such that a first and second phase detector exist. A phase shifter is coupled in a feedback loop of the second phase detector. The output of the phase shifter is coupled to an input of each of the first and the second phase detectors.


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