Self-clocking data entry unit system

Details Self-clocking data entry unit system Self-clocking data entry unit system

1976-01-12

1977-01-18

Yusko,

Communications: electrical

Digital comparator systems

340147SY, 328 63, 179 15AL, 178 691, H04Q 500, H03K 117, H04J 300

Patent

active

040042758

ABSTRACT:
A self-clocking data entry unit system including a plurality of data entry units connected in seris in a loop which is connected at its ends to a controller. Data bits are provided by the controller flowing in one direction through the loop to each of the data entry units, and the data entry units supplant these data bits with new data bits which flow in the same direction through the loop back to the controller. Control bits are interspersed with the data bits, and each of the data bits has an accompanying tag bit that acts as a controlling bit but is of a different type than the first mentioned control bits so that there is a controlling bit of one type or another for each of the bit positions flowing through the loop for controlling the operation of the data entry units and maintaining their operation synchronized with the micro-controller.

REFERENCES:
patent: 3680050 (1972-07-01), Griffin
patent: 3688036 (1972-08-01), Bland
patent: 3781478 (1973-12-01), Blahut et al.
patent: 3893033 (1975-01-01), Finch
patent: 3967062 (1976-06-01), Dobias

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