Self-checking system for electronic processing equipment

Details Self-checking system for electronic processing equipment Self-checking system for electronic processing equipment

1980-01-22

1982-08-31

Atkinson, Charles E.

Excavating

364200, 371 25, G06F 1100

Patent

active

043476082

ABSTRACT:
A central processor controlling a set of peripheral units through an associated logic network is programmed to activate from time to time, through a direct connection by-passing the logic network, a checking unit including a read-only memory storing a variety of microprograms in areas individually addressable by the processor. Upon the reception of a memory address, a timing circuit is set to determine the frequency of stepping pulses advancing a counter which calls forth successive phases of the selected mircroprogram. Code words read out during these phases to the logic network are fed back by the latter to the processor for comparison with corresponding contents of its own program memory; in the event of a disparity, or when failure of the processor to emit a resetting signal lets the counter advance to the limit of its capacity, an alarm indicator is tripped.

REFERENCES:
patent: 3749897 (1973-07-01), Hirvela
patent: 3838264 (1974-09-01), Maker
patent: 4092732 (1978-05-01), Ouchi
patent: 4108359 (1978-08-01), Proto
patent: 4118789 (1978-10-01), Casto et al.
patent: 4142243 (1979-02-01), Bishop et al.
patent: 4251885 (1981-02-01), Dodt et al.

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