Self-checking read and write circuit

Details Self-checking read and write circuit Self-checking read and write circuit

1975-06-27

1976-11-16

Atkinson, Charles E.

Communications: electrical

Digital comparator systems

235153AC, G06F 1100

Patent

active

039926966

ABSTRACT:
A self-checking read and write circuit interfaces a control circuit with a plurality of peripheral circuits. The read and write circuit receives address and data commands from the control circuit, decodes the commands and produces a driving signal to operate relays in the peripheral circuits. The read and write circuit also receives inputs from the peripheral circuits indicating the state thereof, multiplexes and inputs and forwards them to the control circuit under control of address signals. The circuit is self-checking in that a readout multiplexor which scans for state changes in the peripheral circuits has its even parity inputs connected at the outputs of the drive signal decoder and its odd parity inputs connected to the scanned points. A parity check circuit on the multiplexor address leads determines whether the address has even or odd parity. If the parity is even, the output of the multiplexor is compared to the output of the drive signal decoder. If the parity on the address leads is odd, the output of the multiplexor is forwarded to the processor. A single hardware failure in the multiplexor address circuitry causes a failure in one of several modes involving a shift in parity values. These failure modes are detected when the output of the multiplexor is compared to the output of the drive signal decoder.

REFERENCES:
patent: 3401379 (1968-09-01), Prell et al.
patent: 3428945 (1969-02-01), Toy
patent: 3465132 (1969-09-01), Crockett et al.
patent: 3541507 (1970-11-01), Duke
Sellers et al., Error Detection Logic for Digital Computers, McGraw-Hill, 1968, pp. 212-217.

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