Self-checking complementary adder unit

Details Self-checking complementary adder unit Self-checking complementary adder unit

1994-03-22

1996-04-09

Envall, Roy

Boots, shoes, and leggings

364740, 364741, 364788, G06F 1100, G06F 750

Patent

active

055068006

ABSTRACT:
A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits. The compare results are combined by a logic circuit to generate a result check signal.

REFERENCES:
patent: 3986015 (1976-10-01), Gooding et al.
patent: 4982357 (1991-01-01), Bechade
patent: 5018093 (1991-05-01), Shih
IBM Technical Disclosure Bulletin, vol. 13, No. 6, Nov. 1970, "Checked Carry Select Adder", R. B. Freeman.
IBM Technical Disclosure Bulletin, vol. 7, No. 10, Mar. 1965, "Supplemented Parity Checking For A Binary Arithmetic Unit", S. F. Anderson.

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