Coded data generation or conversion – Converter calibration or testing
Patent
1988-04-05
1990-01-30
Shoop, Jr., William M.
Coded data generation or conversion
Converter calibration or testing
341164, 341165, H03M 110
Patent
active
048976504
ABSTRACT:
An analog-to-digital converter macrocell architecture is provided with digital logic for accumulating code-density data for dynamic characterization of the converter. Each macrocell includes an A/D converter (10), a comparator (12), a bin counter (14), a clock counter (16), and a histogram counter (18). the code output of the A/D converter (10) is compared in the comparator (12) with the output of the bin counter (14) and each match increments the histogram counter (18). The histogram counter (18) accumulates code-density data for A/D converter dynamic characterization, these data being read once for every cycle of the clock counter (16).
REFERENCES:
patent: 4335373 (1982-06-01), Sloane
patent: 4340856 (1982-07-01), Orlandi
patent: 4352160 (1982-09-01), Frech et al.
patent: 4354177 (1982-10-01), Sloane
patent: 4371868 (1983-02-01), VandeGrift et al.
patent: 4580126 (1986-04-01), Kato et al.
S. T. Chu et al., "A 20 MHz Flash A/D Converter Macrocell", Proc. of the IEEE Custom Integrated Circuits Conference, May 20-23, 1985, pp. 160-162.
Shott, III James T.
Stokes Edward B.
Davis Jr. James C.
General Electric Company
Shoop Jr. William M.
Snyder Marvin
Williams H. L.
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