Self-cascoding CMOS device

Details Self-cascoding CMOS device Self-cascoding CMOS device

1993-12-01

1995-03-28

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257264, 257268, 257269, 257376, 257391, 257392, 257657, 257205, H01L 2702

Patent

active

054019877

ABSTRACT:
A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 volts less than that of the current sink/source FET to ensure that the current sink/source FET operates in its saturated region. A CMOS structure implementing the self-cascoding transconductance circuit has two doped threshold adjust regions formed beneath a gate electrode such that the two doped threshold adjust regions respectively effectuate the cascode and current sink/source FETs which then share the gate electrode. A method of forming the CMOS structure includes forming two self-cascoding transconductance circuits electrically connected in parallel such that they share a common drain region between their respective gate electrodes, and each has one source region. By forming the two self-cascoding transconductance circuits in such a fashion, the effect of alignment errors contributed by each of the parallel connected self-cascoding transconductance circuits is cancelled out for the combined circuit.

REFERENCES:
patent: 3653978 (1972-04-01), Robinson et al.
patent: 4814839 (1989-03-01), Nishizawa et al.
Allen, P. E. et al., "CMOS Analog Circuit Design," Holt, Rinehart and Winston, Inc., Fort Worth, pp. 413-414 (1987).
Masuda, S. et al., "CMOS Sampled Differential Push-Pull Cascode Operational Amplifier, " IEEE, pp. 1211-1214, (1984).
Geiger, R. L. et al., "VLSI Design Techniques for Analog and Digital Circuits, " MCGraw-Hill New York, pp. 414-427, (1990).

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